From: Stephen Warren <[email protected]> arch/arm/include/asm/arch-tegra*/*.h have accumulated a fair number of unused definitions. This patch aims to delete them all.
While working on this, I noticed a few redundancies and fixed them. No doubt other redundancies still exist simply because I wasn't looking hard for them. A few definitions were moved between files to allow deletion of headers. Later changes will attempt to: - Reduce the number of headers in the include directory. - Move headers into arch/arm/mach-tegra/*, or into the same directory as the drivers they serve. - Eliminate remaining duplication. - Refactor the headers to allow addition of future SoC support, where those SoCs don't share many of the definitions currently located in common headers. Signed-off-by: Stephen Warren <[email protected]> --- arch/arm/include/asm/arch-tegra/ap.h | 69 --------------------- arch/arm/include/asm/arch-tegra/clk_rst.h | 81 +++---------------------- arch/arm/include/asm/arch-tegra/clock.h | 2 +- arch/arm/include/asm/arch-tegra/gp_padctrl.h | 6 +- arch/arm/include/asm/arch-tegra/gpio.h | 4 +- arch/arm/include/asm/arch-tegra/pmc.h | 19 +----- arch/arm/include/asm/arch-tegra/pwm.h | 3 +- arch/arm/include/asm/arch-tegra/sys_proto.h | 4 +- arch/arm/include/asm/arch-tegra/tegra.h | 26 ++------ arch/arm/include/asm/arch-tegra/tegra_i2c.h | 11 +--- arch/arm/include/asm/arch-tegra/tegra_mmc.h | 4 +- arch/arm/include/asm/arch-tegra/timer.h | 15 ----- arch/arm/include/asm/arch-tegra/uart.h | 31 ---------- arch/arm/include/asm/arch-tegra/usb.h | 5 +- arch/arm/include/asm/arch-tegra/warmboot.h | 3 +- arch/arm/include/asm/arch-tegra124/ahb.h | 91 ---------------------------- arch/arm/include/asm/arch-tegra124/display.h | 58 ------------------ arch/arm/include/asm/arch-tegra124/flow.h | 8 +-- arch/arm/include/asm/arch-tegra124/mc.h | 3 +- arch/arm/include/asm/arch-tegra124/tegra.h | 5 +- arch/arm/include/asm/arch-tegra20/tegra.h | 4 +- arch/arm/include/asm/arch-tegra210/ahb.h | 13 +--- arch/arm/include/asm/arch-tegra210/clock.h | 3 +- arch/arm/include/asm/arch-tegra210/flow.h | 16 +---- arch/arm/include/asm/arch-tegra210/mc.h | 5 +- arch/arm/include/asm/arch-tegra210/tegra.h | 5 +- arch/arm/include/asm/arch-tegra30/tegra.h | 4 +- arch/arm/mach-tegra/ap.c | 10 +-- arch/arm/mach-tegra/board.c | 11 ++-- arch/arm/mach-tegra/board2.c | 6 +- arch/arm/mach-tegra/cache.c | 4 +- arch/arm/mach-tegra/clock.c | 4 +- arch/arm/mach-tegra/cpu.h | 34 +++++++---- arch/arm/mach-tegra/emc.c | 5 +- arch/arm/mach-tegra/tegra114/clock.c | 3 +- arch/arm/mach-tegra/tegra124/clock.c | 3 +- arch/arm/mach-tegra/tegra124/cpu.c | 4 +- arch/arm/mach-tegra/tegra124/psci.c | 3 +- arch/arm/mach-tegra/tegra20/clock.c | 3 +- arch/arm/mach-tegra/tegra20/display.c | 5 +- arch/arm/mach-tegra/tegra20/emc.c | 2 +- arch/arm/mach-tegra/tegra20/pmu.c | 4 +- arch/arm/mach-tegra/tegra20/warmboot.c | 4 +- arch/arm/mach-tegra/tegra20/warmboot_avp.c | 6 +- arch/arm/mach-tegra/tegra20/warmboot_avp.h | 6 +- arch/arm/mach-tegra/tegra210/clock.c | 3 +- arch/arm/mach-tegra/tegra30/clock.c | 3 +- board/avionic-design/common/tamonten.c | 9 ++- board/toradex/apalis_t30/apalis_t30.c | 6 +- board/toradex/colibri_t20/colibri_t20.c | 4 +- board/toradex/colibri_t30/colibri_t30.c | 6 +- drivers/i2c/tegra_i2c.c | 6 +- drivers/input/tegra-kbc.c | 5 +- drivers/video/tegra.c | 3 +- include/configs/tegra-common.h | 10 ++- 55 files changed, 117 insertions(+), 553 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/ap.h delete mode 100644 arch/arm/include/asm/arch-tegra/timer.h delete mode 100644 arch/arm/include/asm/arch-tegra/uart.h delete mode 100644 arch/arm/include/asm/arch-tegra124/ahb.h delete mode 100644 arch/arm/include/asm/arch-tegra124/display.h diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h deleted file mode 100644 index 8c2586c6f548..000000000000 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <asm/types.h> - -/* Stabilization delays, in usec */ -#define PLL_STABILIZATION_DELAY (300) -#define IO_STABILIZATION_DELAY (1000) - -#define PLLX_ENABLED (1 << 30) -#define CCLK_BURST_POLICY 0x20008888 -#define SUPER_CCLK_DIVIDER 0x80000000 - -/* Calculate clock fractional divider value from ref and target frequencies */ -#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) - -/* Calculate clock frequency value from reference and clock divider value */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) - -/* AVP/CPU ID */ -#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ -#define PG_UP_TAG_0 0x0 - -/* AP base physical address of internal SRAM */ -#define NV_PA_BASE_SRAM 0x40000000 - -#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) -#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) -#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) - -#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) -#define FLOW_MODE_STOP 2 -#define HALT_COP_EVENT_JTAG (1 << 28) -#define HALT_COP_EVENT_IRQ_1 (1 << 11) -#define HALT_COP_EVENT_FIQ_1 (1 << 9) - -/* This is the main entry into U-Boot, used by the Cortex-A9 */ -extern void _start(void); - -/** - * Works out the SOC/SKU type used for clocks settings - * - * @return SOC type - see TEGRA_SOC... - */ -int tegra_get_chip_sku(void); - -/** - * Returns the pure SOC (chip ID) from the HIDREV register - * - * @return SOC ID - see CHIPID_TEGRAxx... - */ -int tegra_get_chip(void); - -/** - * Returns the SKU ID from the sku_info register - * - * @return SKU ID - see SKU_ID_Txx... - */ -int tegra_get_sku_info(void); - -/* Do any chip-specific cache config */ -void config_cache(void); - -#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) -bool tegra_cpu_is_non_secure(void); -#endif diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index ee9436e2e53d..304e1148cdcd 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2014 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -22,13 +22,6 @@ struct clk_pll_simple { uint pll_misc; /* other misc things */ }; -struct clk_pllm { - uint pllm_base; /* the control register */ - uint pllm_out; /* output control */ - uint pllm_misc1; /* misc1 */ - uint pllm_misc2; /* misc2 */ -}; - /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ struct clk_set_clr { uint set; @@ -246,9 +239,6 @@ struct clk_rst_ctlr { #define PLL_BASE_OVRRIDE_MASK (1U << 28) -#define PLL_LOCK_SHIFT 27 -#define PLL_LOCK_MASK (1U << PLL_LOCK_SHIFT) - /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ #define PLL_OUT_RSTN (1 << 0) #define PLL_OUT_CLKEN (1 << 1) @@ -291,20 +281,7 @@ enum { #define PLLP_OUT4_RSTN_EN (0 << 16) #define PLLP_OUT4_CLKEN (1 << 17) -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ -#define PLLU_POWERDOWN (1 << 16) -#define PLL_ENABLE_POWERDOWN (1 << 14) -#define PLL_ACTIVE_POWERDOWN (1 << 12) - -/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ -#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) -#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) -#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) - /* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */ -#define OSC_XOE_SHIFT 0 -#define OSC_XOE_MASK (1 << OSC_XOE_SHIFT) -#define OSC_XOE_ENABLE (1 << OSC_XOE_SHIFT) #define OSC_XOBP_SHIFT 1 #define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) #define OSC_XOFS_SHIFT 4 @@ -332,65 +309,31 @@ enum { #define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT) /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ -#define SCLK_SYS_STATE_SHIFT 28U -#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) -enum { - SCLK_SYS_STATE_STDBY, - SCLK_SYS_STATE_IDLE, - SCLK_SYS_STATE_RUN, - SCLK_SYS_STATE_IRQ = 4U, - SCLK_SYS_STATE_FIQ = 8U, -}; -#define SCLK_COP_FIQ_MASK (1 << 27) -#define SCLK_CPU_FIQ_MASK (1 << 26) -#define SCLK_COP_IRQ_MASK (1 << 25) -#define SCLK_CPU_IRQ_MASK (1 << 24) +#define SCLK_SYS_STATE_SHIFT 28U +#define SCLK_SYS_STATE_IDLE 1 +#define SCLK_SYS_STATE_RUN 2 #define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12 -#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) #define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8 -#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) #define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4 -#define SCLK_SWAKEUP_RUN_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) #define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0 -#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \ - (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) -enum { - SCLK_SOURCE_CLKM, - SCLK_SOURCE_PLLC_OUT1, - SCLK_SOURCE_PLLP_OUT4, - SCLK_SOURCE_PLLP_OUT3, - SCLK_SOURCE_PLLP_OUT2, - SCLK_SOURCE_CLKD, - SCLK_SOURCE_CLKS, - SCLK_SOURCE_PLLM_OUT1, -}; +#define SCLK_SOURCE_CLKM 0 +#define SCLK_SOURCE_PLLP_OUT4 2 + #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) /* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */ -#define SUPER_SCLK_ENB_SHIFT 31U #define SUPER_SCLK_ENB_MASK (1U << 31) -#define SUPER_SCLK_DIVIDEND_SHIFT 8 -#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT) -#define SUPER_SCLK_DIVISOR_SHIFT 0 -#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT) /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 -#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) #define CLK_SYS_RATE_AHB_RATE_SHIFT 4 -#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) #define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3 -#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) #define CLK_SYS_RATE_APB_RATE_SHIFT 0 -#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) /* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ #define CLR_CPURESET0 (1 << 0) @@ -419,14 +362,6 @@ enum { #define CLR_CPU2_CLK_STP (1 << 10) #define CLR_CPU3_CLK_STP (1 << 11) -/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ -#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) - -/* CRC_CLK_ENB_V_SET_0 0x440 */ -#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) -#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) -#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) - /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ #define PLL_ACTIVE_POWERDOWN (1 << 12) #define PLL_ENABLE_POWERDOWN (1 << 14) diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index e56031d1afa7..a20832b7f35f 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -134,7 +135,6 @@ enum crc_reset_id { /* Things we can hold in reset for each CPU */ crc_rst_cpu = 1, crc_rst_de = 1 << 4, /* What is de? */ - crc_rst_watchdog = 1 << 8, crc_rst_debug = 1 << 12, }; diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h index 695f3e6fba82..854966a30f9e 100644 --- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,8 +8,6 @@ #ifndef _TEGRA_GP_PADCTRL_H_ #define _TEGRA_GP_PADCTRL_H_ -#define GP_HIDREV 0x804 - /* bit fields definitions for APB_MISC_GP_HIDREV register */ #define HIDREV_CHIPID_SHIFT 8 #define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index daf5698e6625..363d16c486d1 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2011, Google Inc. All rights reserved. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,8 +10,6 @@ #define TEGRA_GPIOS_PER_PORT 8 #define TEGRA_PORTS_PER_BANK 4 -#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) -#define GPIO_NAME_SIZE 20 /* gpio_request max label len */ #define GPIO_BANK(x) ((x) >> 5) #define GPIO_PORT(x) (((x) >> 3) & 0x3) diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h index 66c08797656c..9c9b67448985 100644 --- a/arch/arm/include/asm/arch-tegra/pmc.h +++ b/arch/arm/include/asm/arch-tegra/pmc.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -294,7 +294,6 @@ struct pmc_ctlr { #define CRAIL 0 #define CE0 14 #define C0NC 15 -#define SOR 17 #define PMC_XOFS_SHIFT 1 #define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) @@ -319,20 +318,6 @@ struct pmc_ctlr { #define MULT_16 4 #endif -#define AMAP_WRITE_SHIFT 20 -#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) - -/* SEC_DISABLE_0, 0x04 */ -#define SEC_DISABLE_WRITE0_ON (1 << 4) -#define SEC_DISABLE_READ0_ON (1 << 5) -#define SEC_DISABLE_WRITE1_ON (1 << 6) -#define SEC_DISABLE_READ1_ON (1 << 7) -#define SEC_DISABLE_WRITE2_ON (1 << 8) -#define SEC_DISABLE_READ2_ON (1 << 9) -#define SEC_DISABLE_WRITE3_ON (1 << 10) -#define SEC_DISABLE_READ3_ON (1 << 11) -#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) - /* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ #define PWRGATE_TOGGLE_PARTID_CRAIL 0 #define PWRGATE_TOGGLE_PARTID_TD 1 diff --git a/arch/arm/include/asm/arch-tegra/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h index 5a2d9f3a9c1e..b69c0b041f40 100644 --- a/arch/arm/include/asm/arch-tegra/pwm.h +++ b/arch/arm/include/asm/arch-tegra/pwm.h @@ -2,6 +2,7 @@ * Tegra pulse width frequency modulator definitions * * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,8 +16,6 @@ struct pwm_ctlr { uint reserved[3]; /* Space space */ }; -#define PWM_NUM_CHANNELS 4 - /* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */ #define PWM_ENABLE_SHIFT 31 #define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT) diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h b/arch/arm/include/asm/arch-tegra/sys_proto.h index b64f9d813b0e..8c2f94b578fe 100644 --- a/arch/arm/include/asm/arch-tegra/sys_proto.h +++ b/arch/arm/include/asm/arch-tegra/sys_proto.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -8,8 +8,6 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -void invalidate_dcache(void); - /** * tegra_board_id() - Get the board iD * diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 3add1b3c09bb..4051a7d26630 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -8,6 +8,8 @@ #ifndef _TEGRA_H_ #define _TEGRA_H_ +/* AP base physical address of internal SRAM */ +#define NV_PA_BASE_SRAM 0x40000000 #define NV_PA_ARM_PERIPHBASE 0x50040000 #define NV_PA_PG_UP_BASE 0x60000000 #define NV_PA_TMRUS_BASE 0x60005010 @@ -22,17 +24,8 @@ #define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200) #define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300) #define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400) -#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000) -#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) -#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400) -#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600) -#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800) -#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00) -#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00) -#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00) #define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000) #define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400) -#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400) #define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800) #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \ defined(CONFIG_TEGRA114) @@ -40,19 +33,11 @@ #else #define NV_PA_CSITE_BASE 0x70800000 #endif -#define TEGRA_USB_ADDR_MASK 0xFFFFC000 -#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE -#define LOW_LEVEL_SRAM_STACK 0x4000FFFC -#define EARLY_AVP_STACK (NV_PA_SDRAM_BASE + 0x20000) -#define EARLY_CPU_STACK (EARLY_AVP_STACK - 4096) +#define PG_UP_TAG_0 0x0 #define PG_UP_TAG_AVP 0xAAAAAAAA #ifndef __ASSEMBLY__ -struct timerus { - unsigned int cntr_1us; -}; - /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */ #define NV_WB_RUN_ADDRESS 0x40020000 @@ -96,9 +81,8 @@ enum { TEGRA_SOC_CNT, TEGRA_SOC_UNKNOWN = -1, }; +#endif -#else /* __ASSEMBLY__ */ #define PRM_RSTCTRL NV_PA_PMC_BASE -#endif #endif /* TEGRA_H */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 341df74d777d..eb83af89f7f5 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -1,7 +1,7 @@ /* * NVIDIA Tegra I2C controller * - * Copyright 2010-2011 NVIDIA Corporation + * Copyright 2010-2016 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0 */ @@ -18,11 +18,7 @@ enum { enum i2c_transaction_flags { I2C_IS_WRITE = 0x1, /* for I2C write operation */ - I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ - I2C_USE_REPEATED_START = 0x4, /* for repeat start */ - I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ - I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ - I2C_NO_STOP = 0x20, + I2C_USE_REPEATED_START = 0x2, /* for repeat start */ }; /* Contians the I2C transaction details */ @@ -38,7 +34,6 @@ struct i2c_trans_info { * the slave device. */ u8 *buf; - int is_10bit_address; }; struct i2c_control { @@ -142,8 +137,6 @@ struct i2c_ctlr { #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) /* I2C_CLK_DIVISOR_REGISTER */ -#define CLK_DIV_STD_FAST_MODE 0x19 -#define CLK_DIV_HS_MODE 1 #define CLK_MULT_STD_FAST_MODE 8 /** diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index a20bdaa61872..9b371add1de4 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -1,7 +1,7 @@ /* + * Copyright (C) 2011-2016 NVIDIA Corporation * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang <[email protected]> - * Portions Copyright (C) 2011-2012 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,7 +15,6 @@ /* for mmc_config definition */ #include <mmc.h> -#ifndef __ASSEMBLY__ struct tegra_mmc { unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ @@ -145,5 +144,4 @@ struct mmc_host { void pad_init_mmc(struct mmc_host *host); -#endif /* __ASSEMBLY__ */ #endif /* __TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/timer.h b/arch/arm/include/asm/arch-tegra/timer.h deleted file mode 100644 index 5d5664115f41..000000000000 --- a/arch/arm/include/asm/arch-tegra/timer.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* Tegra20 timer functions */ - -#ifndef _TEGRA_TIMER_H -#define _TEGRA_TIMER_H - -/* returns the current monotonic timer value in microseconds */ -unsigned long timer_get_us(void); - -#endif diff --git a/arch/arm/include/asm/arch-tegra/uart.h b/arch/arm/include/asm/arch-tegra/uart.h deleted file mode 100644 index fef7f8db3f98..000000000000 --- a/arch/arm/include/asm/arch-tegra/uart.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _UART_H_ -#define _UART_H_ - -/* UART registers */ -struct uart_ctlr { - uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ - uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ - uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ - uint uart_lcr; /* UART_LCR_0, offset 0C */ - uint uart_mcr; /* UART_MCR_0, offset 10 */ - uint uart_lsr; /* UART_LSR_0, offset 14 */ - uint uart_msr; /* UART_MSR_0, offset 18 */ - uint uart_spr; /* UART_SPR_0, offset 1C */ - uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ - uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ - uint uart_asr; /* UART_ASR_0, offset 3C */ -}; - -#define NVRM_PLLP_FIXED_FREQ_KHZ 216000 -#define NV_DEFAULT_DEBUG_BAUD 115200 - -#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ - -#endif /* UART_H */ diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h index f400c01a3954..24198e4a33d0 100644 --- a/arch/arm/include/asm/arch-tegra/usb.h +++ b/arch/arm/include/asm/arch-tegra/usb.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (c) 2013 NVIDIA Corporation + * Copyright (c) 2013-2016 NVIDIA Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -355,7 +355,4 @@ struct usb_ctlr { #define VBUS_B_SESS_VLD_SW_VALUE (1 << 12) #define VBUS_B_SESS_VLD_SW_EN (1 << 11) -/* Setup USB on the board */ -int usb_process_devicetree(const void *blob); - #endif /* _TEGRA_USB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h index 2e66e0f23b9b..b6326c8f7b11 100644 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ b/arch/arm/include/asm/arch-tegra/warmboot.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010, 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -127,7 +127,6 @@ union scratch3_reg { int warmboot_save_sdram_params(void); int warmboot_prepare_code(u32 seg_address, u32 seg_length); -int sign_data_block(u8 *source, u32 length, u8 *signature); void wb_start(void); /* Start of WB assembly code */ void wb_end(void); /* End of WB assembly code */ diff --git a/arch/arm/include/asm/arch-tegra124/ahb.h b/arch/arm/include/asm/arch-tegra124/ahb.h deleted file mode 100644 index 4e48c43bbf3f..000000000000 --- a/arch/arm/include/asm/arch-tegra124/ahb.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _TEGRA124_AHB_H_ -#define _TEGRA124_AHB_H_ - -struct ahb_ctlr { - u32 reserved0; /* 00h */ - u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */ - u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */ - u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */ - u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */ - u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */ - u32 reserved6[2]; /* 18h, 1ch */ - u32 gizmo_usb; /* _GIZMO_USB_0, 20h */ - u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */ - u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */ - u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */ - u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */ - u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */ - u32 reserved13[2]; /* 38h, 3ch */ - u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */ - u32 reserved15; /* 44h */ - u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */ - u32 reserved17; /* 4ch */ - u32 gizmo_se; /* _GIZMO_SE_0, 50h */ - u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */ - u32 reserved20[3]; /* 58h, 5ch, 60h */ - u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */ - u32 reserved22[3]; /* 68h, 6ch, 70h */ - u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */ - u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */ - u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */ - u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */ - u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */ - u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */ - u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */ - u32 reserved30[13]; /* 90h ~ c0h */ - u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */ - u32 reserved32[5]; /* c8h ~ d8h */ - u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */ - u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */ - u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */ - u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */ - u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */ - u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */ - u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */ - u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */ - /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */ - u32 arbitration_ahb_mem_wrque_mst_id; - u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */ - u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */ - u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */ - u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */ - u32 reserved46[4]; /* 110h ~ 11ch */ - u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */ - u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */ - u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */ - u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */ - u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */ - u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */ - /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */ - u32 axicif_fastsync0_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */ - u32 axicif_fastsync1_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */ - u32 axicif_fastsync2_cpuclk_to_mcclk; - /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */ - u32 axicif_fastsync0_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */ - u32 axicif_fastsync1_mcclk_to_cpuclk; - /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */ - u32 axicif_fastsync2_mcclk_to_cpuclk; -}; - -#define PPSB_STOPCLK_ENABLE (1 << 2) - -#define GIZ_ENABLE_SPLIT (1 << 0) -#define GIZ_ENB_FAST_REARB (1 << 2) -#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) - -#define GIZ_USB_IMMEDIATE (1 << 18) - -/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ -#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) - -#endif /* _TEGRA124_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/display.h b/arch/arm/include/asm/arch-tegra124/display.h deleted file mode 100644 index ca6644af345b..000000000000 --- a/arch/arm/include/asm/arch-tegra124/display.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_TEGRA_DISPLAY_H -#define __ASM_ARCH_TEGRA_DISPLAY_H - -/** - * Register a new display based on device tree configuration. - * - * The frame buffer can be positioned by U-Boot or overriden by the fdt. - * You should pass in the U-Boot address here, and check the contents of - * struct fdt_disp_config to see what was actually chosen. - * - * @param blob Device tree blob - * @param default_lcd_base Default address of LCD frame buffer - * @return 0 if ok, -1 on error (unsupported bits per pixel) - */ -int tegra_display_probe(const void *blob, void *default_lcd_base); - -/** - * Return the current display configuration - * - * @return pointer to display configuration, or NULL if there is no valid - * config - */ -struct fdt_disp_config *tegra_display_get_config(void); - -/** - * Perform the next stage of the LCD init if it is time to do so. - * - * LCD init can be time-consuming because of the number of delays we need - * while waiting for the backlight power supply, etc. This function can - * be called at various times during U-Boot operation to advance the - * initialization of the LCD to the next stage if sufficient time has - * passed since the last stage. It keeps track of what stage it is up to - * and the time that it is permitted to move to the next stage. - * - * The final call should have wait=1 to complete the init. - * - * @param blob fdt blob containing LCD information - * @param wait 1 to wait until all init is complete, and then return - * 0 to return immediately, potentially doing nothing if it is - * not yet time for the next init. - */ -int tegra_lcd_check_next_stage(const void *blob, int wait); - -/** - * Set up the maximum LCD size so we can size the frame buffer. - * - * @param blob fdt blob containing LCD information - */ -void tegra_lcd_early_init(const void *blob); - -#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ diff --git a/arch/arm/include/asm/arch-tegra124/flow.h b/arch/arm/include/asm/arch-tegra124/flow.h index 7818b1bd3455..3f70fb190527 100644 --- a/arch/arm/include/asm/arch-tegra124/flow.h +++ b/arch/arm/include/asm/arch-tegra124/flow.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2013 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -35,14 +35,8 @@ struct flow_ctlr { }; /* HALT_COP_EVENTS_0, 0x04 */ -#define EVENT_MSEC (1 << 24) -#define EVENT_USEC (1 << 25) -#define EVENT_JTAG (1 << 28) #define EVENT_MODE_STOP (2 << 29) -/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ -#define ACTIVE_LP (1 << 0) - /* CPUn_CSR_0 */ #define CSR_ENABLE (1 << 0) #define CSR_IMMEDIATE_WAKE (1 << 3) diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index d97b2c87c631..190dd9754ef1 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -66,7 +66,6 @@ struct mc_ctlr { #define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) -#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) #endif /* _TEGRA124_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/tegra.h b/arch/arm/include/asm/arch-tegra124/tegra.h index db3d8379203b..f009925611c6 100644 --- a/arch/arm/include/asm/arch-tegra124/tegra.h +++ b/arch/arm/include/asm/arch-tegra124/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -23,8 +23,5 @@ #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ #define MAX_NUM_CPU 4 -#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) - -#define TEGRA_USB1_BASE 0x7D000000 #endif /* _TEGRA124_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h index 22774abb936d..1cea245e4171 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010,2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,8 +13,6 @@ #include <asm/arch-tegra/tegra.h> -#define TEGRA_USB1_BASE 0xC5000000 - #define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */ #define MAX_NUM_CPU 2 diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h b/arch/arm/include/asm/arch-tegra210/ahb.h index 3a37af417748..2e676a436e3d 100644 --- a/arch/arm/include/asm/arch-tegra210/ahb.h +++ b/arch/arm/include/asm/arch-tegra210/ahb.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -77,15 +77,4 @@ struct ahb_ctlr { u32 axicif_fastsync2_mcclk_to_cpuclk; }; -#define PPSB_STOPCLK_ENABLE (1 << 2) - -#define GIZ_ENABLE_SPLIT (1 << 0) -#define GIZ_ENB_FAST_REARB (1 << 2) -#define GIZ_DONT_SPLIT_AHB_WR (1 << 7) - -#define GIZ_USB_IMMEDIATE (1 << 18) - -/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */ -#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2) - #endif /* _TEGRA210_AHB_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/include/asm/arch-tegra210/clock.h index 3501be2abbb4..54e70439952d 100644 --- a/arch/arm/include/asm/arch-tegra210/clock.h +++ b/arch/arm/include/asm/arch-tegra210/clock.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -20,7 +20,6 @@ #define PLLC_RESET 30 #define PLLC_IDDQ 27 #define PLLD_ENABLE_CLK 21 -#define PLLD_EN_LCKDET 28 int tegra_plle_enable(void); diff --git a/arch/arm/include/asm/arch-tegra210/flow.h b/arch/arm/include/asm/arch-tegra210/flow.h index e2301aee548f..e4ede6a81500 100644 --- a/arch/arm/include/asm/arch-tegra210/flow.h +++ b/arch/arm/include/asm/arch-tegra210/flow.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -28,18 +28,4 @@ struct flow_ctlr { u32 ram_repair; /* offset 0x40 */ }; -/* HALT_COP_EVENTS_0, 0x04 */ -#define EVENT_MSEC (1 << 24) -#define EVENT_USEC (1 << 25) -#define EVENT_JTAG (1 << 28) -#define EVENT_MODE_STOP (2 << 29) - -/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ -#define ACTIVE_LP (1 << 0) - -/* CPUn_CSR_0 */ -#define CSR_ENABLE (1 << 0) -#define CSR_IMMEDIATE_WAKE (1 << 3) -#define CSR_WAIT_WFI_SHIFT 8 - #endif /* _TEGRA210_FLOW_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h index 77e9aa51f60f..dc910b9c7a0f 100644 --- a/arch/arm/include/asm/arch-tegra210/mc.h +++ b/arch/arm/include/asm/arch-tegra210/mc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016 NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -64,9 +64,6 @@ struct mc_ctlr { u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ }; -#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) - -#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) #endif /* _TEGRA210_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h index 95c67fbb8e9f..17b9f6af3679 100644 --- a/arch/arm/include/asm/arch-tegra210/tegra.h +++ b/arch/arm/include/asm/arch-tegra210/tegra.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -25,8 +25,5 @@ #define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */ #define MAX_NUM_CPU 4 -#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8) - -#define TEGRA_USB1_BASE 0x7D000000 #endif /* _TEGRA210_TEGRA_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index 280245e98e87..28f9741a1d76 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -12,8 +12,6 @@ #include <asm/arch-tegra/tegra.h> -#define TEGRA_USB1_BASE 0x7D000000 - #define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */ #define MAX_NUM_CPU 4 diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index a4fa00c9adae..336a7e08196d 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -1,9 +1,9 @@ /* -* (C) Copyright 2010-2015 -* NVIDIA Corporation <www.nvidia.com> -* + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> + * * SPDX-License-Identifier: GPL-2.0+ -*/ + */ /* Tegra AP (Application Processor) code */ @@ -12,13 +12,13 @@ #include <asm/io.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/mc.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/clock.h> #include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/scu.h> #include <asm/arch-tegra/tegra.h> #include <asm/arch-tegra/warmboot.h> +#include "cpu.h" int tegra_get_chip(void) { diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 3d1d26d13d13..098547ab1e88 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2015 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,7 +14,6 @@ #include <asm/arch/funcmux.h> #include <asm/arch/mc.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/sys_proto.h> @@ -77,7 +76,7 @@ static phys_size_t query_sdram_size(void) emem_cfg = readl(&mc->mc_emem_cfg); #if defined(CONFIG_TEGRA20) debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg); - size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024); + size_bytes = get_ram_size((void *)NV_PA_SDRAM_BASE, emem_cfg * 1024); #else debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg); #ifndef CONFIG_PHYS_64BIT @@ -101,8 +100,8 @@ static phys_size_t query_sdram_size(void) * avoid using it. There's no reason we should need this * validation step anyway. */ - if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024)) - size_bytes = get_ram_size((void *)PHYS_SDRAM_1, + if (emem_cfg <= (0 - NV_PA_SDRAM_BASE) / (1024 * 1024)) + size_bytes = get_ram_size((void *)NV_PA_SDRAM_BASE, size_bytes); #endif } diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 141d6e1cb555..33e346017a8b 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,12 +17,10 @@ #include <asm/arch/pinmux.h> #include <asm/arch/pmu.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/sys_proto.h> -#include <asm/arch-tegra/uart.h> #include <asm/arch-tegra/warmboot.h> #include <asm/arch-tegra/gpu.h> #ifdef CONFIG_TEGRA_CLOCK_SCALING diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 6dad40325d2f..b93814fcb96b 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -8,8 +8,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch/gp_padctrl.h> +#include "cpu.h" #ifndef CONFIG_ARM64 void config_cache(void) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index c50d56dc888b..80d6fccf2551 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0 */ @@ -11,10 +11,8 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h> diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 3f38969a44f1..c0284ce03787 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -21,20 +21,12 @@ #error "Unknown Tegra chip!" #endif -#define PLLX_ENABLED (1 << 30) #define CCLK_BURST_POLICY 0x20008888 #define SUPER_CCLK_DIVIDER 0x80000000 /* Calculate clock fractional divider value from ref and target frequencies */ #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) -/* Calculate clock frequency value from reference and clock divider value */ -#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) - -/* AVP/CPU ID */ -#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ -#define PG_UP_TAG_0 0x0 - #define CORESIGHT_UNLOCK 0xC5ACCE55 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) @@ -53,10 +45,6 @@ #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) -/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */ -#define SB_AA64_RESET_LOW 0x6000C230 -#define SB_AA64_RESET_HIGH 0x6000C234 - struct clk_pll_table { u16 n; u16 m; @@ -71,8 +59,28 @@ void init_pllx(void); void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); +/** + * Returns the pure SOC (chip ID) from the HIDREV register + * + * @return SOC ID - see CHIPID_TEGRAxx... + */ int tegra_get_chip(void); +/** + * Returns the SKU ID from the sku_info register + * + * @return SKU ID - see SKU_ID_Txx... + */ int tegra_get_sku_info(void); +/** + * Works out the SOC/SKU type used for clocks settings + * + * @return SOC type - see TEGRA_SOC... + */ int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); void pmic_enable_cpu_vdd(void); +/* Do any chip-specific cache config */ +void config_cache(void); +#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) +bool tegra_cpu_is_non_secure(void); +#endif diff --git a/arch/arm/mach-tegra/emc.c b/arch/arm/mach-tegra/emc.c index 8c62f36a7b04..70aec7fc1b3d 100644 --- a/arch/arm/mach-tegra/emc.c +++ b/arch/arm/mach-tegra/emc.c @@ -1,19 +1,20 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include "emc.h" #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> #include <asm/arch/pmu.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/sys_proto.h> +#include "emc.h" +#include "cpu.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index e6ef873c8dc4..7a73e159a7cd 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,7 +13,6 @@ #include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h> diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 1e71146236e9..1219b6413844 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,7 +13,6 @@ #include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h> diff --git a/arch/arm/mach-tegra/tegra124/cpu.c b/arch/arm/mach-tegra/tegra124/cpu.c index 0aca6583bacd..be31cb4ac881 100644 --- a/arch/arm/mach-tegra/tegra124/cpu.c +++ b/arch/arm/mach-tegra/tegra124/cpu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -7,14 +7,12 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/ahb.h> #include <asm/arch/clock.h> #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> -#include <asm/arch-tegra/ap.h> #include "../cpu.h" /* Tegra124-specific CPU init code */ diff --git a/arch/arm/mach-tegra/tegra124/psci.c b/arch/arm/mach-tegra/tegra124/psci.c index 16d196508c6e..08225e32dbd4 100644 --- a/arch/arm/mach-tegra/tegra124/psci.c +++ b/arch/arm/mach-tegra/tegra124/psci.c @@ -1,6 +1,7 @@ /* * (C) Copyright 2015, Siemens AG * Author: Jan Kiszka <[email protected]> + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,8 +11,8 @@ #include <asm/psci.h> #include <asm/arch/flow.h> #include <asm/arch/powergate.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/pmc.h> +#include "../cpu.h" static void park_cpu(void) { diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index cd9fb9a55340..0ff538830abd 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,7 +14,6 @@ #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h> diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/tegra20/display.c index 73be9a9cbd1f..52a476eb7d8a 100644 --- a/arch/arm/mach-tegra/tegra20/display.c +++ b/arch/arm/mach-tegra/tegra20/display.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -12,5 +12,4 @@ #include <asm/arch/display.h> #include <asm/arch-tegra/dc.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> diff --git a/arch/arm/mach-tegra/tegra20/emc.c b/arch/arm/mach-tegra/tegra20/emc.c index ed2462ab0fa6..eab61b7cd2ab 100644 --- a/arch/arm/mach-tegra/tegra20/emc.c +++ b/arch/arm/mach-tegra/tegra20/emc.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,7 +8,6 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/apb_misc.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> diff --git a/arch/arm/mach-tegra/tegra20/pmu.c b/arch/arm/mach-tegra/tegra20/pmu.c index a774246a2779..0da704cd4f3c 100644 --- a/arch/arm/mach-tegra/tegra20/pmu.c +++ b/arch/arm/mach-tegra/tegra20/pmu.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,9 +10,9 @@ #include <tps6586x.h> #include <asm/io.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/tegra_i2c.h> #include <asm/arch-tegra/sys_proto.h> +#include "../cpu.h" #define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */ #define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */ diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 5fdc4bbb5007..1013441d4265 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010 - 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,12 +14,12 @@ #include <asm/arch/pinmux.h> #include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/warmboot.h> +#include "crypto.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c index 27ce5f480f54..616358b657be 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010 - 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -11,11 +11,11 @@ #include <asm/arch/flow.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> +#include "../cpu.h" #include "warmboot_avp.h" #define DEBUG_RESET_CORESIGHT @@ -204,7 +204,7 @@ void wb_start(void) reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 | SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 | - SCLK_SYS_STATE_IDLE; + (SCLK_SYS_STATE_IDLE << SCLK_SYS_STATE_SHIFT); writel(reg, &clkrst->crc_sclk_brst_pol); /* avp_resume: no return after the write */ diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h index 7b86acb15632..85892b023fad 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot_avp.h +++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010, 2011 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -12,9 +12,6 @@ #define TEGRA_DEV_H 1 #define TEGRA_DEV_U 2 -#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) -#define SIMPLE_PLLE (CLOCK_ID_EPCI - CLOCK_ID_FIRST_SIMPLE) - #define TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) #define TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) @@ -49,7 +46,6 @@ #define PLLM_OUT1_CLKEN_ENABLE (1 << 1) #define PLLM_OUT1_RATIO_VAL_8 (8 << 8) -#define SCLK_SYS_STATE_IDLE (1 << 28) #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index f0052e7934a1..b025711acf09 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2013-2015 + * (C) Copyright 2013-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -14,7 +14,6 @@ #include <asm/arch/sysctr.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h> diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 1f104f288e57..98289b8ac7a7 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2015 + * (C) Copyright 2010-2016 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -13,7 +13,6 @@ #include <asm/arch/clock.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/timer.h> #include <div64.h> #include <fdtdec.h> diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 9c8677943ad3..981862ce1aff 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -1,8 +1,8 @@ /* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * (C) Copyright 2011-2012 - * Avionic Design GmbH <www.avionic-design.de> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2011-2012 + * Avionic Design GmbH <www.avionic-design.de> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,7 +18,6 @@ #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/sys_proto.h> -#include <asm/arch-tegra/uart.h> #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 3f56971a13b1..8fdee023ee8a 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -1,6 +1,7 @@ /* - * (C) Copyright 2014 - * Marcel Ziswiler <[email protected]> + * (C) Copyright 2014 + * Marcel Ziswiler <[email protected]> + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,6 @@ #include <common.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> #include <asm/io.h> diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 879f25a5384b..b9f845a09b6a 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2012 Lucas Stach + * Copyright (C) 2012 Lucas Stach + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,6 @@ #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/board.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 44b5beb92832..3902bff203d5 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -1,6 +1,7 @@ /* - * (C) Copyright 2014 - * Stefan Agner <[email protected]> + * (C) Copyright 2014 + * Stefan Agner <[email protected]> + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +9,6 @@ #include <common.h> #include <asm/arch/gp_padctrl.h> #include <asm/arch/pinmux.h> -#include <asm/arch-tegra/ap.h> #include <asm/arch-tegra/tegra.h> #include <asm/gpio.h> #include <asm/io.h> diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 2fa07f9c57c4..0735ea0b2b12 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Copyright (c) 2010-2011 NVIDIA Corporation - * NVIDIA Corporation <www.nvidia.com> + * Copyright (c) 2010-2016 NVIDIA Corporation + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -292,7 +292,6 @@ static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, if (end_with_repeated_start) trans_info.flags |= I2C_USE_REPEATED_START; trans_info.num_bytes = len; - trans_info.is_10bit_address = 0; error = send_recv_packets(i2c_bus, &trans_info); if (error) @@ -311,7 +310,6 @@ static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, trans_info.buf = data; trans_info.flags = 0; trans_info.num_bytes = len; - trans_info.is_10bit_address = 0; error = send_recv_packets(i2c_bus, &trans_info); if (error) diff --git a/drivers/input/tegra-kbc.c b/drivers/input/tegra-kbc.c index c77f61076962..349d95804201 100644 --- a/drivers/input/tegra-kbc.c +++ b/drivers/input/tegra-kbc.c @@ -1,6 +1,6 @@ /* - * (C) Copyright 2011 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -16,7 +16,6 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch-tegra/timer.h> #include <linux/input.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 7fd10e6af35e..13b10645478e 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -1,5 +1,7 @@ /* * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -17,7 +19,6 @@ #include <asm/arch/pinmux.h> #include <asm/arch/pwm.h> #include <asm/arch/display.h> -#include <asm/arch-tegra/timer.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index b07ee5645bb8..776394151661 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2010-2012 - * NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2010-2016 + * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -84,7 +84,7 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) +#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRAM_BASE + 0x600000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) #ifndef CONFIG_ARM64 @@ -97,11 +97,9 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_BASE NV_PA_SDRAM_BASE #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ -- 2.8.1 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
