From: Siva Durga Prasad Paladugu <siva.durga.palad...@xilinx.com>
Disable internal clock by clearing the internal
clock enable bit. This bit needs to be cleared too
when we stop the SDCLK for changing the frequency
divisor. This bit should be set to zero when the
device is not using the Host controller.
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---
drivers/mmc/sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index ef7e6150f933..73f05b712f89 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -303,7 +303,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int
clock)
}
reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
- reg &= ~SDHCI_CLOCK_CARD_EN;
+ reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
if (clock == 0)
--
1.9.1
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