Hi Peng,

On 04/05/2016 09:27, Peng Fan wrote:
> From: Peng Fan <peng....@nxp.com>
> 
> According PL310 TRM, Auxiliary Control Register
> "
> The register must be written to using a secure access, and it can be
> read using either a secure or a NS access. If you write to this register
> with a NS access, it results in a write response with a DECERR response,
> and the register is not updated. Writing to this register with the L2
> cache enabled, that is, bit[0] of L2 Control Register set to 1,
> results in a SLVERR.
> "
> 
> So If L2 cache is already enabled by ROM, chaning value of ACR
> will cause SLVERR and uboot hang.
> 
> Signed-off-by: Peng Fan <peng....@nxp.com>
> Cc: Stefano Babic <sba...@denx.de>
> Cc: Fabio Estevam <fabio.este...@nxp.com>
> ---
>  arch/arm/imx-common/cache.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
> index 54b021c..b775488 100644
> --- a/arch/arm/imx-common/cache.c
> +++ b/arch/arm/imx-common/cache.c
> @@ -43,6 +43,12 @@ void v7_outer_cache_enable(void)
>  
>  
>       /*
> +      * Must disable the L2 before changing the latency parameters
> +      * and auxiliary control register.
> +      */
> +     clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
> +
> +     /*
>        * Set bit 22 in the auxiliary control register. If this bit
>        * is cleared, PL310 treats Normal Shared Non-cacheable
>        * accesses as Cacheable no-allocate.
> @@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
>       }
>  #endif
>  
> -     /* Must disable the L2 before changing the latency parameters */
> -     clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
> -
>       writel(0x132, &pl310->pl310_tag_latency_ctrl);
>       writel(0x132, &pl310->pl310_data_latency_ctrl);
>  
> 

It should be fine to have in release, I think.

Acked-by : Stefano Babic <sba...@denx.de>

Best regards,
Stefano Babic

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