Since BayTrail, Intel starts to use new GPIO IPs in their chipset. This adds the GPIO ASL, so that OS can load corresponding drivers for it. On Linux, this is BayTrail pinctrl driver.
Signed-off-by: Bin Meng <[email protected]> --- Changes in v2: - New patch to add GPIO ASL description arch/x86/include/asm/arch-baytrail/acpi/gpio.asl | 95 ++++++++++++++++++++++ .../include/asm/arch-baytrail/acpi/platform.asl | 3 + 2 files changed, 98 insertions(+) create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/gpio.asl diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl new file mode 100644 index 0000000..ef340f3 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl @@ -0,0 +1,95 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng <[email protected]> + * + * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* SouthCluster GPIO */ +Device (GPSC) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 1) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_SC_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} + +/* NorthCluster GPIO */ +Device (GPNC) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 2) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_NC_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} + +/* SUS GPIO */ +Device (GPSS) +{ + Name(_HID, "INT33FC") + Name(_CID, "INT33FC") + Name(_UID, 3) + + Name(RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0, 0x1000, RMEM) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,) + { + GPIO_SUS_IRQ + } + }) + + Method(_CRS) + { + CreateDwordField(^RBUF, ^RMEM._BAS, RBAS) + Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + Return (^RBUF) + } + + Method(_STA) + { + Return (STA_VISIBLE) + } +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl index bd72842..6bc82ec 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -27,6 +27,9 @@ Method(_WAK, 1) Scope (\_SB) { #include "southcluster.asl" + + /* ACPI devices */ + #include "gpio.asl" } /* Chipset specific sleep states */ -- 1.8.2.1 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
