On Mon, May 23, 2016 at 01:31:19PM +0530, Lokesh Vutla wrote: > All the output clock parameters of a DPLL needs to be programmed before > locking the DPLL. But it is being configured after locking the DPLL which > could potentially bypass DPLL. So fixing this sequence. > > Reported-by: Richard Woodruff <[email protected]> > Signed-off-by: Lokesh Vutla <[email protected]> > Reviewed-by: Nishanth Menon <[email protected]>
Applied to u-boot/master, thanks! -- Tom
signature.asc
Description: Digital signature
_______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
