From: Mingkai Hu <mingkai...@nxp.com>
Data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
Signed-off-by: Mingkai Hu <mingkai...@nxp.com>
Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com>
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 670e323..735dd67 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -81,6 +81,11 @@ reset:
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
+ /* Enalbe SMPEN bit */
+ mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
+ orr x0, x0, #0x40
+ msr S3_1_c15_c2_1, x0
+
/* Apply ARM core specific erratas */
bl apply_core_errata
--
2.1.0.27.g96db324
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
