Hi Stefan, On Mon, Jul 18, 2016 at 4:24 PM, Stefan Roese <s...@denx.de> wrote: > This patch adds support for the DFI BayTrail BT700 QSeven SoM installed > on the DFI Q7X-151 baseboard. The baseboard is equipped with the Nuvoton > NCT6102D Super IO chip providing the UART as console. > > Signed-off-by: Stefan Roese <s...@denx.de> > Reviewed-by: Simon Glass <s...@chromium.org> > Cc: Bin Meng <bmeng...@gmail.com> > --- > v2: > - Added missing text to Kconfig entry > > arch/x86/Kconfig | 4 + > arch/x86/dts/Makefile | 1 + > arch/x86/dts/dfi-bt700-q7x-151.dts | 22 +++ > arch/x86/dts/dfi-bt700.dtsi | 309 > ++++++++++++++++++++++++++++++ > board/dfi/Kconfig | 29 +++ > board/dfi/dfi-bt700/Kconfig | 28 +++ > board/dfi/dfi-bt700/MAINTAINERS | 8 + > board/dfi/dfi-bt700/Makefile | 8 + > board/dfi/dfi-bt700/acpi/mainboard.asl | 13 ++ > board/dfi/dfi-bt700/dfi-bt700.c | 30 +++ > board/dfi/dfi-bt700/dsdt.asl | 14 ++ > board/dfi/dfi-bt700/start.S | 9 + > configs/dfi-bt700-internal-uart_defconfig | 61 ++++++ > configs/dfi-bt700-q7x-151_defconfig | 63 ++++++ > include/configs/dfi-bt700.h | 74 +++++++ > 15 files changed, 673 insertions(+) > create mode 100644 arch/x86/dts/dfi-bt700-q7x-151.dts > create mode 100644 arch/x86/dts/dfi-bt700.dtsi > create mode 100644 board/dfi/Kconfig > create mode 100644 board/dfi/dfi-bt700/Kconfig > create mode 100644 board/dfi/dfi-bt700/MAINTAINERS > create mode 100644 board/dfi/dfi-bt700/Makefile > create mode 100644 board/dfi/dfi-bt700/acpi/mainboard.asl > create mode 100644 board/dfi/dfi-bt700/dfi-bt700.c > create mode 100644 board/dfi/dfi-bt700/dsdt.asl > create mode 100644 board/dfi/dfi-bt700/start.S > create mode 100644 configs/dfi-bt700-internal-uart_defconfig > create mode 100644 configs/dfi-bt700-q7x-151_defconfig > create mode 100644 include/configs/dfi-bt700.h > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index 29d1120..5193ee7 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -17,6 +17,9 @@ config VENDOR_CONGATEC > config VENDOR_COREBOOT > bool "coreboot" > > +config VENDOR_DFI > + bool "dfi" > + > config VENDOR_EFI > bool "efi" > > @@ -35,6 +38,7 @@ endchoice > source "board/advantech/Kconfig" > source "board/congatec/Kconfig" > source "board/coreboot/Kconfig" > +source "board/dfi/Kconfig" > source "board/efi/Kconfig" > source "board/emulation/Kconfig" > source "board/google/Kconfig" > diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile > index 4f07f41..ca086bd 100644 > --- a/arch/x86/dts/Makefile > +++ b/arch/x86/dts/Makefile > @@ -9,6 +9,7 @@ dtb-y += bayleybay.dtb \ > conga-qeval20-qa3-e3845.dtb \ > cougarcanyon2.dtb \ > crownbay.dtb \ > + dfi-bt700-q7x-151.dtb \ > efi.dtb \ > galileo.dtb \ > minnowmax.dtb \ > diff --git a/arch/x86/dts/dfi-bt700-q7x-151.dts > b/arch/x86/dts/dfi-bt700-q7x-151.dts > new file mode 100644 > index 0000000..31d9679 > --- /dev/null > +++ b/arch/x86/dts/dfi-bt700-q7x-151.dts > @@ -0,0 +1,22 @@ > +/* > + * Copyright (C) 2014, Bin Meng <bmeng...@gmail.com> > + * Copyright (C) 2016 Stefan Roese <s...@denx.de> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/dts-v1/; > + > +#include "dfi-bt700.dtsi" > + > +#include "serial.dtsi" > + > +/ { > + model = "DFI-BT700"; > + compatible = "dfi,bt700", "intel,baytrail"; > + > + aliases { > + serial0 = &serial; > + spi0 = &spi; > + }; > +}; > diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi > new file mode 100644 > index 0000000..96afc1d > --- /dev/null > +++ b/arch/x86/dts/dfi-bt700.dtsi > @@ -0,0 +1,309 @@ > +/* > + * Copyright (C) 2014, Bin Meng <bmeng...@gmail.com> > + * Copyright (C) 2016 Stefan Roese <s...@denx.de> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <dt-bindings/gpio/x86-gpio.h> > +#include <dt-bindings/interrupt-router/intel-irq.h> > + > +#include "skeleton.dtsi" > +#include "rtc.dtsi" > +#include "tsc_timer.dtsi" > + > +/ { > + config { > + silent_console = <0>; > + }; > + > + pch_pinctrl { > + compatible = "intel,x86-pinctrl"; > + reg = <0 0>; > + > + /* Add UART1 PAD configuration (SIO HS-UART) */ > + uart1_txd@0 { > + pad-offset = <0x10>; > + mode-func = <1>; > + }; > + > + uart1_rxd@0 { > + pad-offset = <0x20>; > + mode-func = <1>; > + }; > + > + /* > + * As of today, the latest version FSP (gold4) for BayTrail > + * misses the PAD configuration of the SD controller's Card > + * Detect signal. The default PAD value for the CD pin sets > + * the pin to work in GPIO mode, which causes card detect > + * status cannot be reflected by the Present State register > + * in the SD controller (bit 16 & bit 18 are always zero). > + * > + * Configure this pin to function 1 (SD controller). > + */ > + sdmmc3_cd@0 { > + pad-offset = <0x3a0>; > + mode-func = <1>; > + }; > + }; > + > + chosen { > + stdout-path = "/serial"; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "intel,baytrail-cpu"; > + reg = <0>; > + intel,apic-id = <0>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "intel,baytrail-cpu"; > + reg = <1>; > + intel,apic-id = <2>; > + }; > + > + cpu@2 { > + device_type = "cpu"; > + compatible = "intel,baytrail-cpu"; > + reg = <2>; > + intel,apic-id = <4>; > + }; > + > + cpu@3 { > + device_type = "cpu"; > + compatible = "intel,baytrail-cpu"; > + reg = <3>; > + intel,apic-id = <6>; > + }; > + }; > + > + pci { > + compatible = "intel,pci-baytrail", "pci-x86"; > + #address-cells = <3>; > + #size-cells = <2>; > + u-boot,dm-pre-reloc; > + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 > + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 > + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; > + > + pciuart0: uart@1e,3 { > + compatible = "pci8086,0f0a.00", > + "pci8086,0f0a", > + "pciclass,070002", > + "pciclass,0700", > + "ns16550", > + "baytrail-hs-uart";
This compatible string is no longer needed. > + u-boot,dm-pre-reloc; > + reg = <0x0200f310 0x0 0x0 0x0 0x0>; > + reg-shift = <2>; > + clock-frequency = <58982400>; > + current-speed = <115200>; > + }; > + > + pch@1f,0 { > + reg = <0x0000f800 0 0 0 0>; > + compatible = "pci8086,0f1c", "intel,pch9"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + irq-router { > + compatible = "intel,irq-router"; > + intel,pirq-config = "ibase"; > + intel,ibase-offset = <0x50>; > + intel,actl-addr = <0>; > + intel,pirq-link = <8 8>; > + intel,pirq-mask = <0xdee0>; > + intel,pirq-routing = < > + /* BayTrail PCI devices */ > + PCI_BDF(0, 2, 0) INTA PIRQA > + PCI_BDF(0, 3, 0) INTA PIRQA > + PCI_BDF(0, 16, 0) INTA PIRQA > + PCI_BDF(0, 17, 0) INTA PIRQA > + PCI_BDF(0, 18, 0) INTA PIRQA > + PCI_BDF(0, 19, 0) INTA PIRQA > + PCI_BDF(0, 20, 0) INTA PIRQA > + PCI_BDF(0, 21, 0) INTA PIRQA > + PCI_BDF(0, 22, 0) INTA PIRQA > + PCI_BDF(0, 23, 0) INTA PIRQA > + PCI_BDF(0, 24, 0) INTA PIRQA > + PCI_BDF(0, 24, 1) INTC PIRQC > + PCI_BDF(0, 24, 2) INTD PIRQD > + PCI_BDF(0, 24, 3) INTB PIRQB > + PCI_BDF(0, 24, 4) INTA PIRQA > + PCI_BDF(0, 24, 5) INTC PIRQC > + PCI_BDF(0, 24, 6) INTD PIRQD > + PCI_BDF(0, 24, 7) INTB PIRQB > + PCI_BDF(0, 26, 0) INTA PIRQA > + PCI_BDF(0, 27, 0) INTA PIRQA > + PCI_BDF(0, 28, 0) INTA PIRQA > + PCI_BDF(0, 28, 1) INTB PIRQB > + PCI_BDF(0, 28, 2) INTC PIRQC > + PCI_BDF(0, 28, 3) INTD PIRQD > + PCI_BDF(0, 29, 0) INTA PIRQA > + PCI_BDF(0, 30, 0) INTA PIRQA > + PCI_BDF(0, 30, 1) INTD PIRQD > + PCI_BDF(0, 30, 2) INTB PIRQB > + PCI_BDF(0, 30, 3) INTC PIRQC > + PCI_BDF(0, 30, 4) INTD PIRQD > + PCI_BDF(0, 30, 5) INTB PIRQB > + PCI_BDF(0, 31, 3) INTB PIRQB > + > + /* > + * PCIe root ports downstream > + * interrupts > + */ > + PCI_BDF(1, 0, 0) INTA PIRQA > + PCI_BDF(1, 0, 0) INTB PIRQB > + PCI_BDF(1, 0, 0) INTC PIRQC > + PCI_BDF(1, 0, 0) INTD PIRQD > + PCI_BDF(2, 0, 0) INTA PIRQB > + PCI_BDF(2, 0, 0) INTB PIRQC > + PCI_BDF(2, 0, 0) INTC PIRQD > + PCI_BDF(2, 0, 0) INTD PIRQA > + PCI_BDF(3, 0, 0) INTA PIRQC > + PCI_BDF(3, 0, 0) INTB PIRQD > + PCI_BDF(3, 0, 0) INTC PIRQA > + PCI_BDF(3, 0, 0) INTD PIRQB > + PCI_BDF(4, 0, 0) INTA PIRQD > + PCI_BDF(4, 0, 0) INTB PIRQA > + PCI_BDF(4, 0, 0) INTC PIRQB > + PCI_BDF(4, 0, 0) INTD PIRQC > + >; > + }; > + > + spi: spi { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "intel,ich9-spi"; > + spi-flash@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0>; > + compatible = "stmicro,n25q064a", > + "spi-flash"; > + memory-map = <0xff800000 0x00800000>; > + rw-mrc-cache { > + label = "rw-mrc-cache"; > + reg = <0x006f0000 0x00010000>; > + }; > + }; > + }; > + > + gpioa { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0 0x20>; > + bank-name = "A"; > + }; > + > + gpiob { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0x20 0x20>; > + bank-name = "B"; > + }; > + > + gpioc { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0x40 0x20>; > + bank-name = "C"; > + }; > + > + gpiod { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0x60 0x20>; > + bank-name = "D"; > + }; > + > + gpioe { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0x80 0x20>; > + bank-name = "E"; > + }; > + > + gpiof { > + compatible = "intel,ich6-gpio"; > + u-boot,dm-pre-reloc; > + reg = <0xA0 0x20>; > + bank-name = "F"; > + }; > + }; > + }; > + > + fsp { > + compatible = "intel,baytrail-fsp"; > + fsp,mrc-init-tseg-size = <0>; > + fsp,mrc-init-mmio-size = <0x800>; > + fsp,mrc-init-spd-addr1 = <0xa0>; > + fsp,mrc-init-spd-addr2 = <0xa2>; > + fsp,emmc-boot-mode = <1>; > + fsp,enable-sdio; > + fsp,enable-sdcard; > + fsp,enable-hsuart0; > + fsp,enable-hsuart1; > + fsp,enable-spi; > + fsp,enable-sata; > + fsp,sata-mode = <1>; > + fsp,enable-lpe; > + fsp,lpss-sio-enable-pci-mode; > + fsp,enable-dma0; > + fsp,enable-dma1; > + fsp,enable-i2c0; > + fsp,enable-i2c1; > + fsp,enable-i2c2; > + fsp,enable-i2c3; > + fsp,enable-i2c4; > + fsp,enable-i2c5; > + fsp,enable-i2c6; > + fsp,enable-pwm0; > + fsp,enable-pwm1; > + fsp,igd-dvmt50-pre-alloc = <2>; > + fsp,aperture-size = <2>; > + fsp,gtt-size = <2>; > + fsp,scc-enable-pci-mode; > + fsp,os-selection = <4>; > + fsp,emmc45-ddr50-enabled; > + fsp,emmc45-retune-timer-value = <8>; > + fsp,enable-igd; > + fsp,enable-memory-down; > + fsp,memory-down-params { > + compatible = "intel,baytrail-fsp-mdp"; > + fsp,dram-speed = <2>; /* 2=1333MHz */ > + fsp,dram-type = <1>; /* 1=DDR3L */ > + fsp,dimm-0-enable; > + fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ > + fsp,dimm-density = <3>; /* 3=8Gbit */ > + fsp,dimm-bus-width = <3>; /* 3=64bits */ > + fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b > */ > + > + /* These following values might need a re-visit */ > + fsp,dimm-tcl = <8>; > + fsp,dimm-trpt-rcd = <8>; > + fsp,dimm-twr = <8>; > + fsp,dimm-twtr = <4>; > + fsp,dimm-trrd = <6>; > + fsp,dimm-trtp = <4>; > + fsp,dimm-tfaw = <22>; > + }; > + }; > + > + microcode { > + update@0 { > +#include "microcode/m0130673325.dtsi" > + }; > + update@1 { > +#include "microcode/m0130679907.dtsi" > + }; > + }; > +}; > diff --git a/board/dfi/Kconfig b/board/dfi/Kconfig > new file mode 100644 > index 0000000..25d0a11 > --- /dev/null > +++ b/board/dfi/Kconfig > @@ -0,0 +1,29 @@ > +# > +# Copyright (C) 2015, Bin Meng <bmeng...@gmail.com> > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +if VENDOR_DFI > + > +choice > + prompt "Mainboard model" > + optional > + > +config TARGET_DFI_BT700 > + bool "DFI BT700 BayTrail" > + help > + This is the DFI Q7X-151 baseboard equipped with the > + DFI BayTrail Bt700 SoM. It contains an Atom E3845 with > + Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2, > + USB 3, SATA, serial console and DisplayPort video out. > + It requires some binary blobs - see README.x86 for details. > + > + Note that PCIE_ECAM_BASE is set up by the FSP so the value used > + by U-Boot matches that value. > + > +endchoice > + > +source "board/dfi/dfi-bt700/Kconfig" > + > +endif > diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig > new file mode 100644 > index 0000000..3f0acb3 > --- /dev/null > +++ b/board/dfi/dfi-bt700/Kconfig > @@ -0,0 +1,28 @@ > +if TARGET_DFI_BT700 > + > +config SYS_BOARD > + default "dfi-bt700" > + > +config SYS_VENDOR > + default "dfi" > + > +config SYS_SOC > + default "baytrail" > + > +config SYS_CONFIG_NAME > + default "dfi-bt700" > + > +config SYS_TEXT_BASE > + default 0xfff00000 if !EFI_STUB > + default 0x01110000 if EFI_STUB > + > +config BOARD_SPECIFIC_OPTIONS # dummy > + def_bool y > + select X86_RESET_VECTOR if !EFI_STUB > + select INTEL_BAYTRAIL > + select BOARD_ROMSIZE_KB_8192 > + > +config PCIE_ECAM_BASE > + default 0xe0000000 > + > +endif > diff --git a/board/dfi/dfi-bt700/MAINTAINERS b/board/dfi/dfi-bt700/MAINTAINERS > new file mode 100644 > index 0000000..9c3d699 > --- /dev/null > +++ b/board/dfi/dfi-bt700/MAINTAINERS > @@ -0,0 +1,8 @@ > +congatec DFI-BT700 > +M: Stefan Roese <s...@denx.de> > +S: Maintained > +F: board/dfi/dfi-bt700 > +F: include/configs/dfi-bt700.h > +F: configs/dfi-bt700-q7x-151_defconfig > +F: arch/x86/dts/dfi-bt700.dtsi > +F: arch/x86/dts/dfi-bt700-q7x-151.dts > diff --git a/board/dfi/dfi-bt700/Makefile b/board/dfi/dfi-bt700/Makefile > new file mode 100644 > index 0000000..8052f5e > --- /dev/null > +++ b/board/dfi/dfi-bt700/Makefile > @@ -0,0 +1,8 @@ > +# > +# Copyright (C) 2015, Google, Inc > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += dfi-bt700.o start.o > +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o > diff --git a/board/dfi/dfi-bt700/acpi/mainboard.asl > b/board/dfi/dfi-bt700/acpi/mainboard.asl > new file mode 100644 > index 0000000..544a049 > --- /dev/null > +++ b/board/dfi/dfi-bt700/acpi/mainboard.asl > @@ -0,0 +1,13 @@ > +/* > + * Copyright (C) 2016, Bin Meng <bmeng...@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/* Power Button */ > +Device (PWRB) > +{ > + Name(_HID, EISAID("PNP0C0C")) > +} > + > +/* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */ > diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c > new file mode 100644 > index 0000000..5701969 > --- /dev/null > +++ b/board/dfi/dfi-bt700/dfi-bt700.c > @@ -0,0 +1,30 @@ > +/* > + * Copyright (C) 2016 Stefan Roese <s...@denx.de> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <nuvoton_nct6102d.h> > +#include <asm/gpio.h> > +#include <asm/ibmpc.h> > +#include <asm/pnp_def.h> > + > +int board_early_init_f(void) > +{ > +#ifdef CONFIG_INTERNAL_UART > + /* Disable the legacy UART which is enabled per default */ > + nct6102d_uarta_disable(); > +#else > + /* > + * The FSP enables the BayTrail internal legacy UART (again). > + * Disable it again, so that the Winbond one can be used. Winbond -> Nuvoton > + */ > + setup_internal_uart(0); > +#endif > + > + /* Disable the watchdog which is enabled per default */ > + nct6102d_wdt_disable(); > + > + return 0; > +} [snip] Other than that, Reviewed-by: Bin Meng <bmeng...@gmail.com> Regards, Bin _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot