Wolfgang Grandegger <w...@grandegger.com> wrote on 16/09/2009 13:45:03: > > Joakim Tjernlund wrote: > > Wolfgang Grandegger <w...@denx.de> wrote on 16/09/2009 12:22:05: > >> Joakim Tjernlund wrote: > >>>> Timur Tabi <ti...@freescale.com> wrote on 15/09/2009 21:04:47: > >>>>> Joakim Tjernlund wrote: > >>>>> > >>>>>> No, the impact on speed from DFSR is pretty small so it will > >>>>>> be close enough. > >>>>> How small? > >>>> From the app note: > >>>> divisor = B * (A + ((3*C)/B)*2); > >>>> > >>>> C is dfsr and 10 <= A <= 30, 16 <= B <= 2048 > >>>> Considering the actual speed may be way lower the requested speed > >>>> I think this is small enough. > >>> Once we have the new procedure in place, we can calculate the exact > >>> divisor so the need for extra CONFIG_ options goes away. > >> As Timur pointed out, a new table/algorithm would require some real > >> testing and also some feedback from the users. Who knows if "your" > >> values do not make trouble. Therefore I vote for using custom > >> settings for maximum flexibility: > >> > >> CONFIG_FSL_I2C_CUSTOM_FDR > >> CONFIG_FSL_I2C_CUSTOM_DFSR > > > > Oh well, since you both wanted it I added it. > > Sent 3 patches, the last patch impl. the latest AN2819 spec. > > > > Would you mind test it a little? > > OK, I will do some tests later this week. What CPU do you use and at > what I2C bus frequency do you test?
mpc8321, I2C bus is between 34KHz and 100KHz, CSB is 133.332 MHz _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
