From: Stephen Warren <swar...@nvidia.com>
In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that. It is unconditionally selected by CONFIG_TEGRA186
since virtually any Tegra186 build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swar...@nvidia.com>
---
arch/arm/mach-tegra/Kconfig | 2 ++
drivers/reset/Kconfig | 7 ++++
drivers/reset/Makefile | 1 +
drivers/reset/tegra186-reset.c | 76 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 86 insertions(+)
create mode 100644 drivers/reset/tegra186-reset.c
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index e8186d515856..1eaf40627254 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -66,10 +66,12 @@ config TEGRA186
bool "Tegra186 family"
select CLK
select DM_MAILBOX
+ select DM_RESET
select MISC
select TEGRA186_BPMP
select TEGRA186_CLOCK
select TEGRA186_GPIO
+ select TEGRA186_RESET
select TEGRA_ARMV8_COMMON
select TEGRA_HSP
select TEGRA_IVC
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0fe8cc3827f1..5b84f2178b71 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -20,4 +20,11 @@ config SANDBOX_RESET
simply accepts requests to reset various HW modules without actually
doing anything beyond a little error checking.
+config TEGRA186_RESET
+ bool "Enable Tegra186 BPMP-based reset driver"
+ depends on TEGRA186_BPMP
+ help
+ Enable support for manipulating Tegra's on-SoC reset signals via IPC
+ requests to the BPMP (Boot and Power Management Processor).
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 71f3b219613e..ff0e0907758b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_DM_RESET) += reset-uclass.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
+obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c
new file mode 100644
index 000000000000..47bc6b843fea
--- /dev/null
+++ b/drivers/reset/tegra186-reset.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <reset-uclass.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+#include <asm/arch-tegra/tegra186_bpmp.h>
+
+static int tegra186_reset_request(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int tegra186_reset_free(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return 0;
+}
+
+static int tegra186_reset_common(struct reset_ctl *reset_ctl,
+ enum mrq_reset_commands cmd)
+{
+ struct mrq_reset_request req;
+
+ req.cmd = cmd;
+ req.reset_id = reset_ctl->id;
+
+ return tegra186_bpmp_call(reset_ctl->dev->parent, MRQ_RESET,
+ &req, sizeof(req), NULL, 0);
+}
+
+static int tegra186_reset_assert(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT);
+}
+
+static int tegra186_reset_deassert(struct reset_ctl *reset_ctl)
+{
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
+ reset_ctl->dev, reset_ctl->id);
+
+ return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT);
+}
+
+struct reset_ops tegra186_reset_ops = {
+ .request = tegra186_reset_request,
+ .free = tegra186_reset_free,
+ .rst_assert = tegra186_reset_assert,
+ .rst_deassert = tegra186_reset_deassert,
+};
+
+static int tegra186_reset_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tegra186_reset) = {
+ .name = "tegra186_reset",
+ .id = UCLASS_RESET,
+ .probe = tegra186_reset_probe,
+ .ops = &tegra186_reset_ops,
+};
--
2.9.2
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