On 3 August 2016 at 23:41, Stefan Agner <[email protected]> wrote: > From: Stefan Agner <[email protected]> > > The page table is maintained by the CPU, hence it is safe to always > align cache flush to a whole cache line size. This allows to use > mmu_page_table_flush for a single page table, e.g. when configure > only small regions through mmu_set_region_dcache_behaviour. > > Signed-off-by: Stefan Agner <[email protected]> > --- > Changes since v1: > - Move cache line alignment from mmu_page_table_flush to > mmu_set_region_dcache_behaviour > > arch/arm/lib/cache-cp15.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
