From: Stephen Warren <swar...@nvidia.com>
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.
Signed-off-by: Stephen Warren <swar...@nvidia.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
v4: Adapt to new misc_call() return code.
v3: Use misc class call op.
v2: This patch wasn't posted.
---
arch/arm/mach-tegra/Kconfig | 2 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 2 +
drivers/clk/tegra/Kconfig | 6 +++
drivers/clk/tegra/Makefile | 5 ++
drivers/clk/tegra/tegra186-clk.c | 104 +++++++++++++++++++++++++++++++++++++++
6 files changed, 120 insertions(+)
create mode 100644 drivers/clk/tegra/Kconfig
create mode 100644 drivers/clk/tegra/Makefile
create mode 100644 drivers/clk/tegra/tegra186-clk.c
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ec2d8ac6a1a3..e8186d515856 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -64,9 +64,11 @@ config TEGRA210
config TEGRA186
bool "Tegra186 family"
+ select CLK
select DM_MAILBOX
select MISC
select TEGRA186_BPMP
+ select TEGRA186_CLOCK
select TEGRA186_GPIO
select TEGRA_ARMV8_COMMON
select TEGRA_HSP
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 6eee8eb369bf..7dd56738b06a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -20,6 +20,7 @@ config SPL_CLK
setting up clocks within SPL, and allows the same drivers to be
used as U-Boot proper.
+source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3cbdd54f4f3e..463b1d647dc6 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,5 +10,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_SANDBOX) += clk_sandbox.o
obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
+
+obj-y += tegra/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_EXYNOS) += exynos/
diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
new file mode 100644
index 000000000000..659fe022c2af
--- /dev/null
+++ b/drivers/clk/tegra/Kconfig
@@ -0,0 +1,6 @@
+config TEGRA186_CLOCK
+ bool "Enable Tegra186 BPMP-based clock driver"
+ depends on TEGRA186_BPMP
+ help
+ Enable support for manipulating Tegra's on-SoC clocks via IPC
+ requests to the BPMP (Boot and Power Management Processor).
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
new file mode 100644
index 000000000000..f32998ccc27d
--- /dev/null
+++ b/drivers/clk/tegra/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o
diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c
new file mode 100644
index 000000000000..075cb464cf6f
--- /dev/null
+++ b/drivers/clk/tegra/tegra186-clk.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/arch-tegra/bpmp_abi.h>
+
+static ulong tegra186_clk_get_rate(struct clk *clk)
+{
+ struct mrq_clk_request req;
+ struct mrq_clk_response resp;
+ int ret;
+
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id;
+
+ ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+ sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ return resp.clk_get_rate.rate;
+}
+
+static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct mrq_clk_request req;
+ struct mrq_clk_response resp;
+ int ret;
+
+ debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
+ clk->dev, clk->id);
+
+ req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id;
+ req.clk_set_rate.rate = rate;
+
+ ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+ sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ return resp.clk_set_rate.rate;
+}
+
+static int tegra186_clk_en_dis(struct clk *clk,
+ enum mrq_reset_commands cmd)
+{
+ struct mrq_clk_request req;
+ struct mrq_clk_response resp;
+ int ret;
+
+ req.cmd_and_id = (cmd << 24) | clk->id;
+
+ ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
+ sizeof(resp));
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tegra186_clk_enable(struct clk *clk)
+{
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE);
+}
+
+static int tegra186_clk_disable(struct clk *clk)
+{
+ debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
+ clk->id);
+
+ return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE);
+}
+
+static struct clk_ops tegra186_clk_ops = {
+ .get_rate = tegra186_clk_get_rate,
+ .set_rate = tegra186_clk_set_rate,
+ .enable = tegra186_clk_enable,
+ .disable = tegra186_clk_disable,
+};
+
+static int tegra186_clk_probe(struct udevice *dev)
+{
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(tegra186_clk) = {
+ .name = "tegra186_clk",
+ .id = UCLASS_CLK,
+ .probe = tegra186_clk_probe,
+ .ops = &tegra186_clk_ops,
+};
--
2.9.2
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