Hi Simon, > Hi, > > On 12 August 2016 at 08:13, Clemens Gruber > <clemens.gru...@pqgruber.com> wrote: > > Hi, > > > > I just tested the current U-Boot master on my i.MX6Q board and the > > following two warnings showed up on the console: > > > > U-Boot 2016.09-rc1-00377-gb8698a2 > > > > CPU: Freescale i.MX6Q rev1.5 at 792 MHz > > Reset cause: POR > > DRAM: 1 GiB > > CACHE: Misaligned operation at range [4fff0000, 4fff0004] > > CACHE: Misaligned operation at range [4fff0024, 4fff0028] > > > > (But everything works fine, as far as I can tell for now) > > > > I did a git bisect and found out that these two warning messages are > > shown since commit 96e451bfa39b (arm: Show cache warnings in U-Boot > > proper only), where a debug statement was changed to a non-SPL > > warning. > > > > Was this intentional and is this warning something to be worried > > about? > > Yes it means there is an error in the calling code. If you can figure > out who is calling this then it is worth fixing. But also see recent > discussions on the mailing list. Also possibly this patch? > > http://patchwork.ozlabs.org/patch/656474/
Yes, this patch fixes the problem on iMX6. However, as I've pointed out here [1], there are other issues to be aware. [1] https://www.mail-archive.com/u-boot@lists.denx.de/msg221577.html > > > > > If not, we could add a new macro debug_non_spl with debug_cond > > !_SPL_BUILD && DEBUG and use that in check_cache_range. > > > > What do you think? > > I'd rather fix the bugs :-) > > > > > Thanks, > > Clemens > > Regards, > Simon
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