On Sun, Aug 14, 2016 at 10:03 AM, Karl Beldan <[email protected]> wrote: > ATM the rx and tx descriptors are handled as cached memory while they > lie in a dedicated RAM of the SoCs, which is an uncached area. > Removing the said dcache ops, while optimizing the logic and clarifying > the code, also gets rid of most of the check_cache_range() incurred > warnings: > CACHE: Misaligned operation at range > > Signed-off-by: Karl Beldan <[email protected]>
Acked-by: Joe Hershberger <[email protected]> _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
