Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul Burton <paul.bur...@imgtec.com>
---

Changes in v3: None
Changes in v2: None

 arch/mips/Kconfig          | 16 ++++++++++++++++
 arch/mips/cpu/Makefile     |  2 ++
 arch/mips/cpu/cm_init.S    | 45 +++++++++++++++++++++++++++++++++++++++++++++
 arch/mips/cpu/start.S      |  6 ++++++
 arch/mips/include/asm/cm.h | 19 +++++++++++++++++++
 5 files changed, 88 insertions(+)
 create mode 100644 arch/mips/cpu/cm_init.S
 create mode 100644 arch/mips/include/asm/cm.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 21066f0..d1cd6f1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -303,6 +303,22 @@ config MIPS_L1_CACHE_SHIFT
 config DYNAMIC_IO_PORT_BASE
        bool
 
+config MIPS_CM
+       bool
+       help
+         Select this if your system contains a MIPS Coherence Manager and you
+         wish U-Boot to configure it or make use of it to retrieve system
+         information such as cache configuration.
+
+config MIPS_CM_BASE
+       hex
+       default 0x1fbf8000
+       help
+         The physical base address at which to map the MIPS Coherence Manager
+         Global Configuration Registers (GCRs). This should be set such that
+         the GCRs occupy a region of the physical address space which is
+         otherwise unused, or at minimum that software doesn't need to access.
+
 endif
 
 endmenu
diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile
index fc6b455..429fd3a 100644
--- a/arch/mips/cpu/Makefile
+++ b/arch/mips/cpu/Makefile
@@ -7,3 +7,5 @@ extra-y = start.o
 obj-y += time.o
 obj-y += interrupts.o
 obj-y += cpu.o
+
+obj-$(CONFIG_MIPS_CM)  += cm_init.o
diff --git a/arch/mips/cpu/cm_init.S b/arch/mips/cpu/cm_init.S
new file mode 100644
index 0000000..ddcaa49
--- /dev/null
+++ b/arch/mips/cpu/cm_init.S
@@ -0,0 +1,45 @@
+/*
+ * MIPS Coherence Manager (CM) Initialisation
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/addrspace.h>
+#include <asm/asm.h>
+#include <asm/cm.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+
+LEAF(mips_cm_map)
+       /* Config3 must exist for a CM to be present */
+       mfc0            t0, CP0_CONFIG, 1
+       bgez            t0, 2f
+       mfc0            t0, CP0_CONFIG, 2
+       bgez            t0, 2f
+
+       /* Check Config3.CMGCR to determine CM presence */
+       mfc0            t0, CP0_CONFIG, 3
+       and             t0, t0, MIPS_CONF3_CMGCR
+       beqz            t0, 2f
+
+       /* Find the current physical GCR base address */
+1:     MFC0            t0, CP0_CMGCRBASE
+       PTR_SLL         t0, t0, 4
+
+       /* If the GCRs are where we want, we're done */
+       PTR_LI          t1, CONFIG_MIPS_CM_BASE
+       beq             t0, t1, 2f
+
+       /* Move the GCRs to our configured base address */
+       PTR_LI          t2, CKSEG1
+       PTR_ADDU        t0, t0, t2
+       sw              zero, GCR_BASE_UPPER(t0)
+       sw              t1, GCR_BASE(t0)
+
+       /* Re-check the GCR base */
+       b               1b
+
+2:     jr              ra
+       END(mips_cm_map)
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 6f1d219..c157d03 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -141,6 +141,12 @@ reset:
 1:
        PTR_L   gp, 0(ra)
 
+#ifdef CONFIG_MIPS_CM
+       PTR_LA  t9, mips_cm_map
+       jalr    t9
+        nop
+#endif
+
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 # ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
        /* Initialize any external memory */
diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
new file mode 100644
index 0000000..0261733
--- /dev/null
+++ b/arch/mips/include/asm/cm.h
@@ -0,0 +1,19 @@
+/*
+ * MIPS Coherence Manager (CM) Register Definitions
+ *
+ * Copyright (c) 2016 Imagination Technologies Ltd.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#ifndef __MIPS_ASM_CM_H__
+#define __MIPS_ASM_CM_H__
+
+/* Global Control Register (GCR) offsets */
+#define GCR_BASE                       0x0008
+#define GCR_BASE_UPPER                 0x000c
+#define GCR_REV                                0x0030
+
+/* GCR_REV CM versions */
+#define GCR_REV_CM3                    0x0800
+
+#endif /* __MIPS_ASM_CM_H__ */
-- 
2.10.0

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