On 09/21/2016 04:25 AM, Chin Liang See wrote:
> To enable configuration of sdr.ctrlcfg.extratime1 register which enable
> extra clocks for read to write command timing. This is critical to
> ensure successful LPDDR2 interface
> Signed-off-by: Chin Liang See <cl...@altera.com>
> Cc: Marek Vasut <ma...@denx.de>
> Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> ---

Applied all, thanks.

Best regards,
Marek Vasut
U-Boot mailing list

Reply via email to