I have been puzzled by the need to flush external L3 cache for Freescale
Layerscape series SoCs. Flushing L3 requires EL3. It is the case now, but
this may change in the future. Implementing a SMC call to perform this
task is possible but only if necessary. Recent investigation shows we can
flush by virtual address most of the time. The only exception is when
dcache_disable() is called. I think this can be addressed by flushing
the stack U-Boot is using and skip flushing L3 totally.

Once this is proved to work, we can drop flushing L3 all together.

During this investigation, I found the procedure of turning off d-cache
seems wrong. The data is lost if d-cache is off first. I am not sure
if this only happens to Freescale Layerscape SoCs. Wondering why no
one else reports any issue, expecially those SoCs without L3 cache.

York Sun (2):
  armv8: Fix dcache disable function
  armv8: Fix flush_dcache_all function

 arch/arm/cpu/armv8/cache_v8.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)


U-Boot mailing list

Reply via email to