On 10/13/2016 10:33 AM, Chin Liang See wrote:
> Add support for Stratix 10 SoC development kit
>
> Signed-off-by: Chin Liang See <cl...@altera.com>
> Cc: Marek Vasut <ma...@denx.de>
> Cc: Dinh Nguyen <dingu...@opensource.altera.com>
> Cc: Ley Foon Tan <lf...@altera.com>
> Cc: Tien Fong Chee <tfc...@altera.com>
> ---
> arch/arm/Kconfig | 4 +-
> arch/arm/mach-socfpga/Kconfig | 10 ++
> configs/socfpga_stratix10_defconfig | 21 ++++
> include/configs/socfpga_stratix10_socdk.h | 166
> ++++++++++++++++++++++++++++++
> 4 files changed, 200 insertions(+), 1 deletion(-)
> create mode 100644 configs/socfpga_stratix10_defconfig
> create mode 100644 include/configs/socfpga_stratix10_socdk.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 2d3303b..f75010a 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -544,13 +544,15 @@ config ARCH_SNAPDRAGON
>
> config ARCH_SOCFPGA
> bool "Altera SOCFPGA family"
> - select CPU_V7
> + select CPU_V7 if !TARGET_SOCFPGA_STRATIX10
This will fail when stratix86 comes out. You should use select CPU_V7 if
TARGET_SOCFPGA_GEN5 . And this will need adjustment for A10.
> + select ARM64 if TARGET_SOCFPGA_STRATIX10
> select SUPPORT_SPL
> select OF_CONTROL
> select SPL_OF_CONTROL
> select DM
> select DM_SPI_FLASH
> select DM_SPI
> + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
Why do you need this ?
> config TARGET_CM_T43
> bool "Support cm_t43"
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index d91b8bb..12452a9 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -38,6 +38,9 @@ config TARGET_SOCFPGA_CYCLONE5
> config TARGET_SOCFPGA_GEN5
> bool
>
> +config TARGET_SOCFPGA_STRATIX10
> + bool
> +
> choice
> prompt "Altera SOCFPGA board select"
> optional
> @@ -70,6 +73,10 @@ config TARGET_SOCFPGA_SR1500
> bool "SR1500 (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
>
> +config TARGET_SOCFPGA_STRATIX10_SOCDK
> + bool "Altera SOCFPGA SoCDK (Stratix 10)"
> + select TARGET_SOCFPGA_STRATIX10
Is what you are adding really a SoCDK or SoCVT ?
> config TARGET_SOCFPGA_TERASIC_DE0_NANO
> bool "Terasic DE0-Nano-Atlas (Cyclone V)"
> select TARGET_SOCFPGA_CYCLONE5
> @@ -89,11 +96,13 @@ config SYS_BOARD
> default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
> default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
> default "sr1500" if TARGET_SOCFPGA_SR1500
> + default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
> default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
[...]
> +/*
> + * U-Boot environment configurations
> + */
> +#define CONFIG_ENV_IS_NOWHERE 1
> +#define CONFIG_ENV_SIZE 0x1000
Since you support MMC, place the env into MMC .
> +/*
> + * Boot arguments passed to the boot command. The value of
> + * CONFIG_BOOTARGS goes into the environment value "bootargs".
> + * Do note the value will overide also the chosen node in FDT blob.
> + */
> +#define CONFIG_BOOTARGS "rdinit=/sbin/init mem=2048M"
I believe these whole bootargs are bogus, the mem= shouldn't be needed
unless there is a problem with passing this information from u-boot. And
the rdinit is just default value.
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "verify=n\0" \
Is this verify=n needed?
> + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> + "bootimage=Image\0" \
> + "fdt_addr=100\0" \
You should load the FDT onto some more sensible address, not right below
the kernel. Something like loading kernel to +64MB from start
of RAM and fdt to +96M might make sense.
> + "fdtimage=socfpga_stratix10_swvp.dtb\0" \
> + "mmcroot=/dev/mmcblk0p2\0" \
> + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
> + " root=${mmcroot} rw rootwait;" \
> + "booti ${loadaddr} - ${fdt_addr}\0" \
> + "mmcload=mmc rescan;" \
> + "load mmc 0:1 ${loadaddr} ${bootimage};" \
> + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
> +
> +/*
> + * Generic Interrupt Controller Definitions
> + */
> +#define CONFIG_GICV2
> +#define GICD_BASE 0xFFFC1000
> +#define GICC_BASE 0xFFFC2000
This should be in the base address file, no ?
> +/*
> + * External memory configurations
> + */
> +#define PHYS_SDRAM_1 0x0
> +#define PHYS_SDRAM_1_SIZE 0x80000000
> +#define CONFIG_SYS_SDRAM_BASE 0
> +#define CONFIG_NR_DRAM_BANKS 1
> +#define CONFIG_SYS_MEMTEST_START 0
> +#define CONFIG_SYS_MEMTEST_END 0x100000
> +
> +/*
> + * Serial / UART configurations
> + */
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE -4
> +#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
> +#define CONFIG_SYS_NS16550_CLK 1000000
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
I _think_ you can pull those from DT nowadays.
> +/*
> + * Timer & watchdog configurations
> + */
> +#define CONFIG_SYS_TIMERBASE SOCFPGA_SYSTIMER0_ADDRESS
> +#define TIMER_LOAD_VAL 0xFFFFFFFF
> +
> +/*
> + * SDMMC configurations
> + */
> +#ifdef CONFIG_CMD_MMC
> +#define CONFIG_MMC
> +#define CONFIG_BOUNCE_BUFFER
> +#define CONFIG_GENERIC_MMC
> +#define CONFIG_DWMMC
> +#define CONFIG_SOCFPGA_DWMMC
> +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
> +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
Isn't this defined in the socfpga_common.h already ?
> +#endif
> +/*
> + * Flash configurations
> + */
> +#define CONFIG_SYS_MAX_FLASH_BANKS 1
> +#define CONFIG_SYS_NO_FLASH
> +
> +
> +/*
> + * SPL memory layout
> + *
> + * On chip RAM
> + * 0xFFE0_0000 ...... Start of OCRAM
> + * SPL code, rwdata
> + * 0xFFEx_xxxx ...... Top of stack (grows down)
> + * 0xFFEy_yyyy ...... Global Data
> + * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN)
> + * 0xFFE3_FFFF ...... End of OCRAM
> + *
> + * SDRAM
> + * 0x0000_0000 ...... Start of SDRAM_1
> + * unused / empty space for image loading
> + * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE)
> + * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE)
> + * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB)
> + *
> + */
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_RAM_DEVICE
> +#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
> +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
> +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
> +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
> +#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \
> + - CONFIG_SPL_BSS_MAX_SIZE)
> +#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN)
> +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \
> + - CONFIG_SYS_SPL_MALLOC_SIZE)
> +
> +/* SPL SDMMC boot support */
> +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
> +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
> +
> +#endif /* __CONFIG_H */
>
--
Best regards,
Marek Vasut
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