On Sen, 2016-10-17 at 15:42 +0200, Marek Vasut wrote: > On 10/17/2016 03:32 PM, See, Chin Liang wrote: > > > > On Min, 2016-10-16 at 17:33 +0200, Marek Vasut wrote: > > > > > > On 10/13/2016 10:33 AM, Chin Liang See wrote: > > > > > > > > > > > > Separate the Clock Manager to support both GEN5 SoC and > > > > Stratix 10 SoC. > > > > > > > > Signed-off-by: Chin Liang See <cl...@altera.com> > > > > Cc: Marek Vasut <ma...@denx.de> > > > > Cc: Dinh Nguyen <dingu...@opensource.altera.com> > > > > Cc: Ley Foon Tan <lf...@altera.com> > > > > Cc: Tien Fong Chee <tfc...@altera.com> > > > > --- > > > > arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++ > > > > 1 file changed, 8 insertions(+) > > > > > > > > diff --git a/arch/arm/mach-socfpga/clock_manager.c > > > > b/arch/arm/mach- > > > > socfpga/clock_manager.c > > > > index aa71636..0d67b3c 100644 > > > > --- a/arch/arm/mach-socfpga/clock_manager.c > > > > +++ b/arch/arm/mach-socfpga/clock_manager.c > > > > @@ -10,6 +10,7 @@ > > > > > > > > DECLARE_GLOBAL_DATA_PTR; > > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > > > static const struct socfpga_clock_manager *clock_manager_base > > > > = > > > > (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; > > > > > > > > @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void) > > > > > > > > return clock; > > > > } > > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */ > > > > > > > > unsigned int cm_get_mmc_controller_clk_hz(void) > > > > { > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > > > uint32_t reg, clock = 0; > > > > > > > > /* identify the source of MMC clock */ > > > > @@ -475,8 +478,12 @@ unsigned int > > > > cm_get_mmc_controller_clk_hz(void) > > > > /* further divide by 4 as we have fixed divider at > > > > wrapper */ > > > > clock /= 4; > > > > return clock; > > > > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) > > > > + return 25000000; > > > Is this always gonna be the case or is this S10VP specific ? > > > > > > > > > > > > > > > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */ > > > > } > > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > > > unsigned int cm_get_qspi_controller_clk_hz(void) > > > > { > > > > uint32_t reg, clock = 0; > > > > @@ -556,3 +563,4 @@ U_BOOT_CMD( > > > > "display clocks", > > > > "" > > > Why does the clock display not work on S10 ? Are some functions > > > missing? > > Not for SOCVP. But will be added in later stage when testing > > against > > emulation > How hard would it be to add this missing functionality now ? >
That will take weeks as that need to be validated as whole in emulation platform. > > > > > > > > Maybe we should split the clock manager into common part and then > > > gen5 > > > and gen10 specific parts ? > > Ok, we can do that as initially we were worried too many files > > created > > within mach-socfpga. > It's probably better than polluting the clock code with ifdefs. > Ok, we have an consensus then Thanks Chin Liang > [...] > > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot