On Thursday 06 October 2016 04:49 PM, Vignesh R wrote:
> If the write transaction size(write_bytes) is not a multiple of word
> length, then issue word length writes till the we reach the dangling
> bytes. On the final write, issue byte by byte write to complete the
> transaction. This marginally improves write throughput when performing
> random sized writes to the flash.
>
> Signed-off-by: Vignesh R <vigne...@ti.com>
> ---
Gentle ping... Any comments?
>
> Tested on K2G GP EVM.
>
> drivers/spi/cadence_qspi_apb.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index e285d3c1e761..4b891f227243 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -752,10 +752,16 @@ int cadence_qspi_apb_indirect_write_execute(struct
> cadence_spi_platdata *plat,
> while (remaining > 0) {
> write_bytes = remaining > page_size ? page_size : remaining;
> /* Handle non-4-byte aligned access to avoid data abort. */
> - if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
> + if ((uintptr_t)txbuf % 4) {
> writesb(plat->ahbbase, txbuf, write_bytes);
> - else
> + } else {
> writesl(plat->ahbbase, txbuf, write_bytes >> 2);
> + if (write_bytes % 4) {
> + writesb(plat->ahbbase,
> + txbuf + rounddown(write_bytes, 4),
> + write_bytes % 4);
> + }
> + }
>
> ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
> CQSPI_REG_SDRAMLEVEL_WR_MASK <<
>
--
Regards
Vignesh
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