From: Stephen Warren <[email protected]> SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided.
Signed-off-by: Stephen Warren <[email protected]> --- v2: * Implement all dummy/weak functions in assembly, since some cache operations cannot access DRAM/stack. * Rename hook functions with __asm prefix etc. --- arch/arm/cpu/armv8/cache.S | 18 +++++++++++++++--- arch/arm/cpu/armv8/cache_v8.c | 8 +++++--- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ++-- arch/arm/include/asm/system.h | 4 +++- arch/arm/mach-tegra/tegra186/cache.S | 4 ++-- 5 files changed, 27 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 46f25e63f01d..f1deaa723024 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -150,11 +150,23 @@ ENTRY(__asm_invalidate_icache_all) ret ENDPROC(__asm_invalidate_icache_all) -ENTRY(__asm_flush_l3_cache) +ENTRY(__asm_invalidate_l3_dcache) mov x0, #0 /* return status as success */ ret -ENDPROC(__asm_flush_l3_cache) - .weak __asm_flush_l3_cache +ENDPROC(__asm_invalidate_l3_dcache) + .weak __asm_invalidate_l3_dcache + +ENTRY(__asm_flush_l3_dcache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_flush_l3_dcache) + .weak __asm_flush_l3_dcache + +ENTRY(__asm_invalidate_l3_icache) + mov x0, #0 /* return status as success */ + ret +ENDPROC(__asm_invalidate_l3_icache) + .weak __asm_invalidate_l3_icache /* * void __asm_switch_ttbr(ulong new_ttbr) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index cd3f6c10ae12..6c5630c0a84c 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -421,19 +421,20 @@ __weak void mmu_setup(void) void invalidate_dcache_all(void) { __asm_invalidate_dcache_all(); + __asm_invalidate_l3_dcache(); } /* * Performs a clean & invalidation of the entire data cache at all levels. * This function needs to be inline to avoid using stack. - * __asm_flush_l3_cache return status of timeout + * __asm_flush_l3_dcache return status of timeout */ inline void flush_dcache_all(void) { int ret; __asm_flush_dcache_all(); - ret = __asm_flush_l3_cache(); + ret = __asm_flush_l3_dcache(); if (ret) debug("flushing dcache returns 0x%x\n", ret); else @@ -623,7 +624,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, void icache_enable(void) { - __asm_invalidate_icache_all(); + invalidate_icache_all(); set_sctlr(get_sctlr() | CR_I); } @@ -640,6 +641,7 @@ int icache_status(void) void invalidate_icache_all(void) { __asm_invalidate_icache_all(); + __asm_invalidate_l3_icache(); } #else /* CONFIG_SYS_ICACHE_OFF */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 5d0b7a45c354..5700b1fb6543 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -245,7 +245,7 @@ hnf_set_pstate: ret -ENTRY(__asm_flush_l3_cache) +ENTRY(__asm_flush_l3_dcache) /* * Return status in x0 * success 0 @@ -275,7 +275,7 @@ ENTRY(__asm_flush_l3_cache) mov x0, x8 mov lr, x29 ret -ENDPROC(__asm_flush_l3_cache) +ENDPROC(__asm_flush_l3_dcache) #endif #ifdef CONFIG_MP diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index c18e1e3a10ee..5e9a9f850b65 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -93,7 +93,9 @@ void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end); void __asm_invalidate_tlb_all(void); void __asm_invalidate_icache_all(void); -int __asm_flush_l3_cache(void); +int __asm_invalidate_l3_dcache(void); +int __asm_flush_l3_dcache(void); +int __asm_invalidate_l3_icache(void); void __asm_switch_ttbr(u64 new_ttbr); void armv8_switch_to_el2(void); diff --git a/arch/arm/mach-tegra/tegra186/cache.S b/arch/arm/mach-tegra/tegra186/cache.S index d876cd93b432..3ca3f3c8af68 100644 --- a/arch/arm/mach-tegra/tegra186/cache.S +++ b/arch/arm/mach-tegra/tegra186/cache.S @@ -10,7 +10,7 @@ #define SMC_SIP_INVOKE_MCE 0x82FFFF00 #define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) -ENTRY(__asm_flush_l3_cache) +ENTRY(__asm_flush_l3_dcache) mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff) movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16 mov x1, #0 @@ -22,4 +22,4 @@ ENTRY(__asm_flush_l3_cache) smc #0 mov x0, #0 ret -ENDPROC(__asm_flush_l3_cache) +ENDPROC(__asm_flush_l3_dcache) -- 2.10.1 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
