Hi, Stefan Stefan Roese wrote: > This patch merges the ECC handling (ECC parity byte writing) into one > file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx. > This exception is because only those PPC's use the completely different > Denali SDRAM controller core. > > Previously we had two routines to generate/write the ECC parity bytes. > With this patch we now only have one core function left. > > Tested on Kilauea (no ECC) and Katmai (with and without ECC). > > Signed-off-by: Stefan Roese <[email protected]> > Cc: Felix Radensky <[email protected]> > Cc: Grant Erickson <[email protected]> > Cc: Pieter Voorthuijsen <[email protected]> > --- > Pieter, the p3p440 is currently the only PPC4xx DDR based board (non DDR2) > with ECC enabled. Could you please test this patch on the p3p440, and > let me know if you see any problems? > > And Felix & Grant, it would be great if you could test this patch on your > platforms as well. > > Thanks. > >
Patch does not apply. I've tried both u-boot.git and u-boot-ppc4xx.git. Applying ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling error: patch failed: cpu/ppc4xx/44x_spd_ddr2.c:198 error: cpu/ppc4xx/44x_spd_ddr2.c: patch does not apply Patch failed at 0001. After fixing the problem manually I was able to successfully test your patch on 405EXr and 460EX boards with ECC. Thanks a lot. Felix. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
