Hi York, We are not sure yet if we're exactly hitting this core hang issue but we might as well implement the workaround just in case.
Cheers, Darwin ________________________________________ From: york sun <york....@nxp.com> Sent: Saturday, 22 October 2016 9:00 a.m. To: Darwin Dingel; u-boot@lists.denx.de Subject: Re: [PATCH] powerpc/t2080: CPU erratum A-007907 On 10/18/2016 09:28 PM, Darwin Dingel wrote: > Core hang occurs when using L1 stashes. Workaround is to disable L1 > stashes so software uses L2 cache for stashes instead. > This patch is missing the signed-off-by signature from the author. > Reviewed-by: Chris Packham <chris.pack...@alliedtelesis.co.nz> > Cc: York Sun <york....@nxp.com> > --- > arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++- > arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++ > arch/powerpc/include/asm/config_mpc85xx.h | 1 + > arch/powerpc/include/asm/processor.h | 1 + > 4 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c > b/arch/powerpc/cpu/mpc85xx/cmd_errata.c > index 3b06ae4..197eb2f 100644 > --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c > +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c > @@ -329,7 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int > argc, char * const argv[]) > #ifdef CONFIG_SYS_FSL_ERRATUM_A009663 > puts("Work-around for Erratum A009663 enabled\n"); > #endif > - > +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 > + puts("Work-around for Erratum A007907 enabled\n"); > +#endif > return 0; > } > > diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c > b/arch/powerpc/cpu/mpc85xx/cpu_init.c > index 53b3729..0e744f0 100644 > --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c > +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c > @@ -775,6 +775,13 @@ int cpu_init_r(void) > sync(); > } > #endif > + > +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907 > + flush_dcache(); > + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); Have you hit this erratum? Does this workaround seem to be effective? > + sync(); > +#endif > + > #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 > /* > * A-005812 workaround sets bit 32 of SPR 976 for SoCs running > diff --git a/arch/powerpc/include/asm/config_mpc85xx.h > b/arch/powerpc/include/asm/config_mpc85xx.h > index 6d845e8..3d0ce2e 100644 > --- a/arch/powerpc/include/asm/config_mpc85xx.h > +++ b/arch/powerpc/include/asm/config_mpc85xx.h > @@ -910,6 +910,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) > #define CONFIG_SYS_FSL_ERRATUM_A006593 > #define CONFIG_SYS_FSL_ERRATUM_A007186 > #define CONFIG_SYS_FSL_ERRATUM_A006379 > +#define CONFIG_SYS_FSL_ERRATUM_A007907 Can you enable this erratum workaround to T4240 and B4860 as well? York > #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE > #define CONFIG_SYS_FSL_SFP_VER_3_0 > > diff --git a/arch/powerpc/include/asm/processor.h > b/arch/powerpc/include/asm/processor.h > index fdfca90..6f9b297 100644 > --- a/arch/powerpc/include/asm/processor.h > +++ b/arch/powerpc/include/asm/processor.h > @@ -501,6 +501,7 @@ > #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ > #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 > */ > #define L1CSR2_DCWS 0x40000000 /* Data Cache Write > Shadow */ > +#define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */ > #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 > */ > #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ > #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC > Enable */ > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot