On 10/24/2016 01:48 PM, Darwin Dingel wrote:
> Core hang occurs when using L1 stashes. Workaround is to disable L1
> stashes so software uses L2 cache for stashes instead.
>
> Reviewed-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
> Signed-off-by: Darwin Dingel <darwin.din...@alliedtelesis.co.nz>
> Cc: York Sun <york....@nxp.com>
> ---
> Changes for v2:
> - Enabled for T4240 and B4860
>
Thanks for doing this.
The subject should be updated to not specific to T2080, if you respin
this patch for any reason.
> arch/powerpc/cpu/mpc85xx/cmd_errata.c | 4 +++-
> arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 +++++++
> arch/powerpc/include/asm/config_mpc85xx.h | 3 +++
> arch/powerpc/include/asm/processor.h | 1 +
> 4 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> index 3b06ae4..197eb2f 100644
> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> @@ -329,7 +329,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int
> argc, char * const argv[])
> #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
> puts("Work-around for Erratum A009663 enabled\n");
> #endif
> -
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
> + puts("Work-around for Erratum A007907 enabled\n");
> +#endif
> return 0;
> }
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> index 53b3729..0e744f0 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> @@ -775,6 +775,13 @@ int cpu_init_r(void)
> sync();
> }
> #endif
> +
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
> + flush_dcache();
> + mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
> + sync();
> +#endif
> +
My erratum document shows a second step is to insert sync instruction
before each dcbtls CT=0 or dcbtstls CT=0. I only see dcbtls used in
start.S and no referendce to dcbtstls at all. I will consult the design
team to confirm if the second step.
York
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