The A80, having 2 clusters of 4 cores each, has an ARM CCI-400 hardware block for cache coherency.
Add the base address for CCI-400, and also add the base address for CPUCFG. Signed-off-by: Chen-Yu Tsai <[email protected]> --- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index c775bcc515a0..88b48c644c06 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -17,6 +17,9 @@ #define REGS_APB1_BASE 0x07000000 #define REGS_RCPUS_BASE 0x08000000 +#define SUNXI_CPUCFG_BASE 0x01700000 +#define SUNXI_CCI400_BASE 0x01790000 + #define SUNXI_SRAM_D_BASE 0x08100000 /* AHB0 Module */ -- 2.10.2 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
