On 11/15/2016 06:03 AM, Vignesh R wrote: > > > On Sunday 13 November 2016 03:13 AM, Marek Vasut wrote: >> On 11/10/2016 06:18 AM, Vignesh R wrote: >>> According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC >>> TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit >>> data interface writes until the last word of an indirect transfer >>> otherwise indirect writes is known to fails sometimes. So, make sure >>> that QSPI indirect writes are 32 bit sized except for the last write. >>> >>> [1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf >>> >>> Signed-off-by: Vignesh R <[email protected]> >> >> I would if it wouldn't be better to use bounce buffer for the txbuf . >> See common/bouncebuf.c >> > > Yeah, I guess that will also help in implementing DMA support. How about > having a generic implementation of bounce buffer support in > spi_flash_cmd_{read/write}_ops?
We have generic implementation of bounce buffer in common/bouncebuf.c and not everyone needs it. -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
