Those registers are necessary to generate and output the PCIe clock.
Signed-off-by: Lukasz Majewski <[email protected]>
---
arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 ++
arch/arm/include/asm/omap_common.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c
b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index b5f1d70..5a0c872 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -385,6 +385,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_phy_power_sata = 0x4A002374,
.ctrl_core_sma_sw_0 = 0x4A0023FC,
.ctrl_core_sma_sw_1 = 0x4A002534,
+ .ctrl_core_sma_sw_6 = 0x4A003C14,
.control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518,
.control_core_mac_id_1_lo = 0x4A00251C,
@@ -396,6 +397,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_core_mmr_lock5 = 0x4A002550,
.control_core_control_io1 = 0x4A002554,
.control_core_control_io2 = 0x4A002558,
+ .control_core_pcie_power_state = 0x4A0026C0,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
.control_smart1io_padconf_0 = 0x4A002DA8,
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/include/asm/omap_common.h
index bb74321..2d8dbbd 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -393,6 +393,7 @@ struct omap_sys_ctrl_regs {
u32 control_usbotghs_ctrl;
u32 control_phy_power_sata;
u32 control_padconf_core_base;
+ u32 control_core_pcie_power_state;
u32 control_paconf_global;
u32 control_paconf_mode;
u32 control_smart1io_padconf_0;
@@ -482,6 +483,7 @@ struct omap_sys_ctrl_regs {
u32 iodelay_config_base;
u32 ctrl_core_sma_sw_0;
u32 ctrl_core_sma_sw_1;
+ u32 ctrl_core_sma_sw_6;
};
struct dpll_params {
--
2.1.4
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