On 01/06/2017 01:54 AM, Zhiqiang Hou wrote: > From: Mingkai Hu <mingkai...@nxp.com> > > For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is > set. The SMPEN bit should be set before enabling the data cache. > If not enabled, the cache is not coherent with other cores and > data corruption could occur. > > For A57/A72, SMPEN bit enables the processor to receive instruction > cache and TLB maintenance operations broadcast from other processors > in the cluster. This bit should be set before enabling the caches and > MMU, or performing any cache and TLB maintenance operations. > > Signed-off-by: Mingkai Hu <mingkai...@nxp.com> > Signed-off-by: Gong Qianyu <qianyu.g...@nxp.com> > Signed-off-by: Mateusz Kulikowski <mateusz.kulikow...@gmail.com> > Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com> > --- > V2: > - Revised the help information. >
This set is applied to fsl-qoriq master, awaiting upstream. Thanks. York _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
