Hi,

On 16/01/17 07:44, Maxime Ripard wrote:
> On Fri, Jan 13, 2017 at 08:28:07AM +0000, André Przywara wrote:
>> On 13/01/17 08:09, Vishnu Patekar wrote:
>> Hi Vishnu,
>>
>>> Even for the single core cortex-a7, SMP bit should be set before
>>> enabling MMU and cache.
>>>
>>> Reference: Cortex A7 r0p5 TRM. section 4.3.31.
>>
>> Ah, good point, thanks for the heads up. I was misled by the SMP name
>> when answering Icenowy.
>> So it's about coherency in general and we need the bit for TLBs and
>> caches to work as well.
>> Let me check what that means for the other SoCs and whether we need to
>> rename the config symbol then.

So I checked the other ARMv7 Cortex TRMs, in contrast to the A7 TRM they
explicitly speak of cache and TLB requests from other _processors_.
So it should not be needed to use caches and the MMU on a uni-core
implementation (which seem to be pretty rare with Cortex-A7s).
But: my understanding is that it actually controls handling coherency
request from outside of the processor core, which could be from a
coherent agent on the bus as well, if I get this correctly.
So I think it does not hurt to enable the bit on the V3s as well and
could avoid potential problems. As this lines up with what the TRM says,
we should turn it on as in the other cores.

Icenowy: did you see problems with setting this bit and turned it off
for a reason or was that just because the bit is named "SMP"?

> If we still needs it,

First: we definitely need this symbol, since it guards an implementation
defined register and the Cortex-A53 does not define it. So we have to
confine its use to the ARMv7 Cortex CPUs.

> x86 has a CONFIG_SMP symbol, that would be
> better to just leverage that.

Sounds tempting, but this seems to be a generic symbol that enables SMP
support _within_ U-Boot, so it allows multiple cores to execute U-Boot
code. This is clearly not what we want. Defining it seems to enable
architecture specific and generic code paths in U-Boot.

I can rename this symbol if that helps to avoid confusion, for instance
to read CONFIG_SUNXI_NO_ACTLR_SMP or to CONFIG_CPU_IS_NOT_SMP or
CONFIG_CPU_IS_UP.

Cheers,
Andre.

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