On 01/10/2017 06:20 AM, Chee Tien Fong wrote: > From: Tien Fong Chee <[email protected]> > > There is no dependency on doing a separate clrbits first in the > dwmac_deassert_reset function. Combine them into a single > clrsetbits call. > > Signed-off-by: Dinh Nguyen <[email protected]> > Signed-off-by: Tien Fong Chee <[email protected]> > Cc: Marek Vasut <[email protected]> > Cc: Dinh Nguyen <[email protected]> > Cc: Chin Liang See <[email protected]> > Cc: Tien Fong <[email protected]> > --- > arch/arm/mach-socfpga/misc.c | 9 +++------ > 1 file changed, 3 insertions(+), 6 deletions(-) > > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c > index 2645129..c97caea 100644 > --- a/arch/arm/mach-socfpga/misc.c > +++ b/arch/arm/mach-socfpga/misc.c > @@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int > of_reset_id, > return; > } > > - /* Clearing emac0 PHY interface select to 0 */ > - clrbits_le32(&sysmgr_regs->emacgrp_ctrl, > - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); > - > /* configure to PHY interface select choosed */ > - setbits_le32(&sysmgr_regs->emacgrp_ctrl, > - phymode << physhift);
I don't think this patch is correct. The purpose of using these calls separately is so that the write with cleared physel mask actually reaches hardware, followed by read and another write with the physel mask set. clrsetbits will do only one read-modify-write cycle. > + clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, > + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, > + phymode << physhift); > > /* Release the EMAC controller from reset */ > socfpga_per_reset(reset, 0); > -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
