On Wed, Jan 25, 2017 at 02:22:43AM +0000, Andre Przywara wrote: > The DRAM controller in the Allwinner H5 SoC is again very similar to > the one in the H3 and A64. > Based on the existing socid parameter, add support for this controller > by reusing the bulk of the code and only deviating where needed. > These new bits set or cleared here and there have been mostly found by > looking at DRAM register dumps after using the H5 boot0 and comparing > them to what we set in the code. So for now it's mostly unclear what > those bits actually mean - hence the missing names and comments. > Also add the delay line parameters taken from the boot0 and libdram > disassembly. > Register setup differences between H5 and H3 are courtesy of Jens Kuske. > > Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Maxime Ripard <[email protected]> Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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