On Mon, Jan 23, 2017 at 12:05 PM, Marek Vasut <[email protected]> wrote: > On 01/10/2017 06:20 AM, Chee Tien Fong wrote: >> From: Tien Fong Chee <[email protected]> >> >> These compat macros would be used by clock manager and pin mux drivers >> to look the required HW info from DTS for hardware initialization. >> >> Signed-off-by: Tien Fong Chee <[email protected]> >> Cc: Marek Vasut <[email protected]> >> Cc: Dinh Nguyen <[email protected]> >> Cc: Chin Liang See <[email protected]> >> Cc: Tien Fong <[email protected]> >> --- >> include/fdtdec.h | 8 ++++++++ >> lib/fdtdec.c | 8 ++++++++ >> 2 files changed, 16 insertions(+) >> >> diff --git a/include/fdtdec.h b/include/fdtdec.h >> index d074478..73e3a46 100644 >> --- a/include/fdtdec.h >> +++ b/include/fdtdec.h >> @@ -155,6 +155,14 @@ enum fdt_compat_id { >> COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */ >> COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */ >> COMPAT_SUNXI_NAND, /* SUNXI NAND controller */ >> + COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */ >> + COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* pinctrl-single */ > > Um, the comment needs fixing and it needs to be prefixed with SoCFPGA , > all of them. Okay. > > And again, is any of this stuff actually used ? Yes, all are in used. > >> + COMPAT_ALTERA_SOCFPGA_H2F_BRG, /* Arria10 hps2fpga bridge */ >> + COMPAT_ALTERA_SOCFPGA_LWH2F_BRG, /* Arria10 lwhps2fpga bridge */ >> + COMPAT_ALTERA_SOCFPGA_F2H_BRG, /* Arria10 fpga2hps bridge */ >> + COMPAT_ALTERA_SOCFPGA_F2SDR0, /* Arria10 fpga2SDRAM0 bridge >> */ >> + COMPAT_ALTERA_SOCFPGA_F2SDR1, /* Arria10 fpga2SDRAM1 bridge >> */ >> + COMPAT_ALTERA_SOCFPGA_F2SDR2, /* Arria10 fpga2SDRAM2 bridge >> */ >> >> COMPAT_COUNT, >> }; >> diff --git a/lib/fdtdec.c b/lib/fdtdec.c >> index 81f47ef..ebe4a9a 100644 >> --- a/lib/fdtdec.c >> +++ b/lib/fdtdec.c >> @@ -66,6 +66,14 @@ static const char * const compat_names[COMPAT_COUNT] = { >> COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"), >> COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"), >> COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"), >> + COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"), >> + COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"), >> + COMPAT(ALTERA_SOCFPGA_H2F_BRG, "altr,socfpga-hps2fpga-bridge"), >> + COMPAT(ALTERA_SOCFPGA_LWH2F_BRG, "altr,socfpga-lwhps2fpga-bridge"), >> + COMPAT(ALTERA_SOCFPGA_F2H_BRG, "altr,socfpga-fpga2hps-bridge"), >> + COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"), >> + COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"), >> + COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"), >> }; >> >> const char *fdtdec_get_compatible(enum fdt_compat_id id) >> > > > -- > Best regards, > Marek Vasut > _______________________________________________ > U-Boot mailing list > [email protected] > http://lists.denx.de/mailman/listinfo/u-boot _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
