This reverts commit 57897c13de03ac0136d64641a3eab526c6810387. The Cadence QSPI device does not work with caching (introduced with the bounce buffer in this commit) on the Altera SoC platform.
Signed-off-by: Jason A. Rush <[email protected]> --- Changed in v2: None drivers/spi/cadence_qspi_apb.c | 26 ++++++-------------------- include/configs/k2g_evm.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/stv0991.h | 1 - 4 files changed, 6 insertions(+), 23 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e02f2217f4..a6787c3b47 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -30,7 +30,6 @@ #include <linux/errno.h> #include <wait_bit.h> #include <spi.h> -#include <bouncebuf.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US 1 /* 1us */ @@ -735,17 +734,6 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int remaining = n_tx; unsigned int write_bytes; int ret; - struct bounce_buffer bb; - u8 *bb_txbuf; - - /* - * Handle non-4-byte aligned accesses via bounce buffer to - * avoid data abort. - */ - ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ); - if (ret) - return ret; - bb_txbuf = bb.bounce_buffer; /* Configure the indirect read transfer bytes */ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); @@ -756,11 +744,11 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, while (remaining > 0) { write_bytes = remaining > page_size ? page_size : remaining; - writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2); - if (write_bytes % 4) - writesb(plat->ahbbase, - bb_txbuf + rounddown(write_bytes, 4), - write_bytes % 4); + /* Handle non-4-byte aligned access to avoid data abort. */ + if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) + writesb(plat->ahbbase, txbuf, write_bytes); + else + writesl(plat->ahbbase, txbuf, write_bytes >> 2); ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, CQSPI_REG_SDRAMLEVEL_WR_MASK << @@ -770,7 +758,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, goto failwr; } - bb_txbuf += write_bytes; + txbuf += write_bytes; remaining -= write_bytes; } @@ -781,7 +769,6 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, printf("Indirect write completion error (%i)\n", ret); goto failwr; } - bounce_buffer_stop(&bb); /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE, @@ -792,7 +779,6 @@ failwr: /* Cancel the indirect write */ writel(CQSPI_REG_INDIRECTWR_CANCEL, plat->regbase + CQSPI_REG_INDIRECTWR); - bounce_buffer_stop(&bb); return ret; } diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index bd252312a2..a5e72a331b 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -73,7 +73,6 @@ #define CONFIG_CADENCE_QSPI #define CONFIG_CQSPI_REF_CLK 384000000 #define CONFIG_CQSPI_DECODER 0x0 -#define CONFIG_BOUNCE_BUFFER #endif #endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 582b04af3d..a3fa28c791 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -200,7 +200,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() #endif #define CONFIG_CQSPI_DECODER 0 -#define CONFIG_BOUNCE_BUFFER /* * Designware SPI support diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 24dd81856b..5d180d7419 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -71,7 +71,6 @@ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ #define CONFIG_CQSPI_DECODER 0 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 -#define CONFIG_BOUNCE_BUFFER #endif -- 2.11.0 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/listinfo/u-boot
