Load the regbase/ahbbase 'reg' DT properties using the standard dev_get_addr_index function, and add __iomem to all register variables declarations.
Signed-off-by: Jason A. Rush <[email protected]> --- Changed in v2: None drivers/spi/cadence_qspi.c | 25 ++++++++++++++----------- drivers/spi/cadence_qspi.h | 28 ++++++++++++++-------------- drivers/spi/cadence_qspi_apb.c | 24 ++++++++++++------------ 3 files changed, 40 insertions(+), 37 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 9a6e41f330..09f2ec3528 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -40,7 +40,7 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) static int spi_calibration(struct udevice *bus, uint hz) { struct cadence_spi_priv *priv = dev_get_priv(bus); - void *base = priv->regbase; + void __iomem *base = priv->regbase; u8 opcode_rdid = 0x9F; unsigned int idcode = 0, temp = 0; int err = 0, i, range_lo = -1, range_hi = -1; @@ -190,7 +190,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev); - void *base = priv->regbase; + void __iomem *base = priv->regbase; u8 *cmd_buf = priv->cmd_buf; size_t data_bytes; int err = 0; @@ -284,18 +284,21 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) const void *blob = gd->fdt_blob; int node = dev_of_offset(bus); int subnode; - u32 data[4]; - int ret; - /* 2 base addresses are needed, lets get them from the DT */ - ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data)); - if (ret) { - printf("Error: Can't get base addresses (ret=%d)!\n", ret); - return -ENODEV; + /* Load the regbase from the first 'reg' property */ + plat->regbase = (void __iomem *)dev_get_addr_index(bus, 0); + if (IS_ERR(plat->regbase)) { + printf("Error: Can't get regbase address!\n"); + return PTR_ERR(plat->regbase); + } + + /* Load the ahbbase from the second 'reg' property */ + plat->ahbbase = (void __iomem *)dev_get_addr_index(bus, 1); + if (IS_ERR(plat->ahbbase)) { + printf("Error: Can't get ahbbase address!\n"); + return PTR_ERR(plat->ahbbase); } - plat->regbase = (void *)data[0]; - plat->ahbbase = (void *)data[2]; plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); /* All other paramters are embedded in the child node */ diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index d1927a4003..da21b1346d 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -16,8 +16,8 @@ struct cadence_spi_platdata { unsigned int max_hz; - void *regbase; - void *ahbbase; + void __iomem *regbase; + void __iomem *ahbbase; u32 page_size; u32 block_size; @@ -29,8 +29,8 @@ struct cadence_spi_platdata { }; struct cadence_spi_priv { - void *regbase; - void *ahbbase; + void __iomem *regbase; + void __iomem *ahbbase; size_t cmd_len; u8 cmd_buf[32]; size_t data_len; @@ -43,12 +43,12 @@ struct cadence_spi_priv { /* Functions call declaration */ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat); -void cadence_qspi_apb_controller_enable(void *reg_base_addr); -void cadence_qspi_apb_controller_disable(void *reg_base_addr); +void cadence_qspi_apb_controller_enable(void __iomem *reg_base_addr); +void cadence_qspi_apb_controller_disable(void __iomem *reg_base_addr); -int cadence_qspi_apb_command_read(void *reg_base_addr, +int cadence_qspi_apb_command_read(void __iomem *reg_base_addr, unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf); -int cadence_qspi_apb_command_write(void *reg_base_addr, +int cadence_qspi_apb_command_write(void __iomem *reg_base_addr, unsigned int cmdlen, const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf); @@ -61,17 +61,17 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, unsigned int txlen, const u8 *txbuf); -void cadence_qspi_apb_chipselect(void *reg_base, +void cadence_qspi_apb_chipselect(void __iomem *reg_base, unsigned int chip_select, unsigned int decoder_enable); -void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode); -void cadence_qspi_apb_config_baudrate_div(void *reg_base, +void cadence_qspi_apb_set_clk_mode(void __iomem *reg_base, uint mode); +void cadence_qspi_apb_config_baudrate_div(void __iomem *reg_base, unsigned int ref_clk_hz, unsigned int sclk_hz); -void cadence_qspi_apb_delay(void *reg_base, +void cadence_qspi_apb_delay(void __iomem *reg_base, unsigned int ref_clk, unsigned int sclk_hz, unsigned int tshsl_ns, unsigned int tsd2d_ns, unsigned int tchsh_ns, unsigned int tslch_ns); -void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); -void cadence_qspi_apb_readdata_capture(void *reg_base, +void cadence_qspi_apb_enter_xip(void __iomem *reg_base, char xip_dummy); +void cadence_qspi_apb_readdata_capture(void __iomem *reg_base, unsigned int bypass, unsigned int delay); #endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 907c6edf0a..52ec892c4a 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -190,7 +190,7 @@ static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf, return addr; } -void cadence_qspi_apb_controller_enable(void *reg_base) +void cadence_qspi_apb_controller_enable(void __iomem *reg_base) { unsigned int reg; reg = readl(reg_base + CQSPI_REG_CONFIG); @@ -198,7 +198,7 @@ void cadence_qspi_apb_controller_enable(void *reg_base) writel(reg, reg_base + CQSPI_REG_CONFIG); } -void cadence_qspi_apb_controller_disable(void *reg_base) +void cadence_qspi_apb_controller_disable(void __iomem *reg_base) { unsigned int reg; reg = readl(reg_base + CQSPI_REG_CONFIG); @@ -207,7 +207,7 @@ void cadence_qspi_apb_controller_disable(void *reg_base) } /* Return 1 if idle, otherwise return 0 (busy). */ -static unsigned int cadence_qspi_wait_idle(void *reg_base) +static unsigned int cadence_qspi_wait_idle(void __iomem *reg_base) { unsigned int start, count = 0; /* timeout in unit of ms */ @@ -233,7 +233,7 @@ static unsigned int cadence_qspi_wait_idle(void *reg_base) return 0; } -void cadence_qspi_apb_readdata_capture(void *reg_base, +void cadence_qspi_apb_readdata_capture(void __iomem *reg_base, unsigned int bypass, unsigned int delay) { unsigned int reg; @@ -257,7 +257,7 @@ void cadence_qspi_apb_readdata_capture(void *reg_base, cadence_qspi_apb_controller_enable(reg_base); } -void cadence_qspi_apb_config_baudrate_div(void *reg_base, +void cadence_qspi_apb_config_baudrate_div(void __iomem *reg_base, unsigned int ref_clk_hz, unsigned int sclk_hz) { unsigned int reg; @@ -287,7 +287,7 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base, cadence_qspi_apb_controller_enable(reg_base); } -void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode) +void cadence_qspi_apb_set_clk_mode(void __iomem *reg_base, uint mode) { unsigned int reg; @@ -305,7 +305,7 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode) cadence_qspi_apb_controller_enable(reg_base); } -void cadence_qspi_apb_chipselect(void *reg_base, +void cadence_qspi_apb_chipselect(void __iomem *reg_base, unsigned int chip_select, unsigned int decoder_enable) { unsigned int reg; @@ -339,7 +339,7 @@ void cadence_qspi_apb_chipselect(void *reg_base, cadence_qspi_apb_controller_enable(reg_base); } -void cadence_qspi_apb_delay(void *reg_base, +void cadence_qspi_apb_delay(void __iomem *reg_base, unsigned int ref_clk, unsigned int sclk_hz, unsigned int tshsl_ns, unsigned int tsd2d_ns, unsigned int tchsh_ns, unsigned int tslch_ns) @@ -407,7 +407,7 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) cadence_qspi_apb_controller_enable(plat->regbase); } -static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, +static int cadence_qspi_apb_exec_flash_cmd(void __iomem *reg_base, unsigned int reg) { unsigned int retry = CQSPI_REG_RETRY; @@ -438,7 +438,7 @@ static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, } /* For command RDID, RDSR. */ -int cadence_qspi_apb_command_read(void *reg_base, +int cadence_qspi_apb_command_read(void __iomem *reg_base, unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf) { @@ -480,7 +480,7 @@ int cadence_qspi_apb_command_read(void *reg_base, } /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ -int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen, +int cadence_qspi_apb_command_write(void __iomem *reg_base, unsigned int cmdlen, const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf) { unsigned int reg = 0; @@ -793,7 +793,7 @@ failwr: return ret; } -void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy) +void cadence_qspi_apb_enter_xip(void __iomem *reg_base, char xip_dummy) { unsigned int reg; -- 2.11.0 _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/listinfo/u-boot
