Dinh Nguyen wrote: > Hi Jason, > > On 03/01/2017 10:38 AM, Rush, Jason A. wrote: >> Add the 'cdns,trigger-address' property to the cadence QSPI device >> node for Altera SoC devices. >> >> Signed-off-by: Jason A. Rush <[email protected]> >> --- >> Changed in v2: >> - renamed trigger-base to trigger-address >> >> arch/arm/dts/socfpga.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi >> index 8588221e57..ac26d05722 100644 >> --- a/arch/arm/dts/socfpga.dtsi >> +++ b/arch/arm/dts/socfpga.dtsi >> @@ -646,6 +646,7 @@ >> num-cs = <4>; >> fifo-depth = <128>; >> sram-size = <128>; >> + trigger-address = <0x00000000>; > > According to the documentation I see, the indaddrtrig on SoCFPGA is at > offset of 0x1C. >
Yes, the indaddrtrig register is at offset 0x1C, but the 'trigger-address' property is the value written to that address. In older versions of U-Boot (where the CQSPI worked) the value was Written into the indaddrtrig register with the following code: ((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK) ahbbase is 0xffa00000 and the mask is 0xFFFFF, which resulted in writing a 0x0 into the indaddrtrig register. Later changes to the CQSPI code removed that mask, so the indaddrtrig register was programmed with 0xffa00000 which resulted in the CPU resetting whenever a read/write was performed. You can see this same change has been incorporated into the 4.10 kernel: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/socfpga.dtsi?id=refs/tags/v4.10#n727 https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/mtd/spi-nor/cadence-quadspi.c?id=refs/tags/v4.10#n1054 -- Regards, Jason _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/listinfo/u-boot
