Nick Thompson wrote: > Add new directory for da8xx architecture includes. > > Provides initial support for TI OMAP-L1x/DA8xx SoC devices. > See http://www.ti.com > > The DA8xx devices are similar to DaVinci devices but have a differing > memory map and updated peripheral versions. > > Signed-off-by: Nick Thompson <[email protected]> > --- > Applies to u-boot-ti > > include/asm-arm/arch-da8xx/clock.h | 25 ++++ > include/asm-arm/arch-da8xx/emif_defs.h | 71 ++++++++++ > include/asm-arm/arch-da8xx/hardware.h | 221 > ++++++++++++++++++++++++++++++++ > include/asm-arm/arch-da8xx/i2c_defs.h | 93 +++++++++++++ > 4 files changed, 410 insertions(+), 0 deletions(-) > > diff --git a/include/asm-arm/arch-da8xx/clock.h > b/include/asm-arm/arch-da8xx/clock.h > new file mode 100644 > index 0000000..8cb4f51 > --- /dev/null > +++ b/include/asm-arm/arch-da8xx/clock.h > @@ -0,0 +1,25 @@ > +/* > + * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. > <[email protected]> + * > + * DA8xx clock include header > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. > + * > ---------------------------------------------------------------------------- > + */ > + > +/* Included from hardware.h so protect from assembler inclusion */ > +#ifndef __ASSEMBLY__ > +int clk_get(unsigned int id); > +#endif > diff --git a/include/asm-arm/arch-da8xx/emif_defs.h > b/include/asm-arm/arch-da8xx/emif_defs.h
This is exactly the same as davinci > new file mode 100644 > index 0000000..c91e30c > --- /dev/null > +++ b/include/asm-arm/arch-da8xx/emif_defs.h > @@ -0,0 +1,71 @@ > +/* > + * Copyright (C) 2007 Sergey Kubushyn <[email protected]> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > +#ifndef _EMIF_DEFS_H_ > +#define _EMIF_DEFS_H_ > + > +#include <asm/arch/hardware.h> > + > +typedef struct { > + dv_reg ERCSR; dv_reg is hiding that this is volatile pointer. > + dv_reg AWCCR; > + dv_reg SDBCR; > + dv_reg SDRCR; > + dv_reg AB1CR; > + dv_reg AB2CR; > + dv_reg AB3CR; > + dv_reg AB4CR; > + dv_reg SDTIMR; > + dv_reg DDRSR; > + dv_reg DDRPHYCR; > + dv_reg DDRPHYSR; > + dv_reg TOTAR; > + dv_reg TOTACTR; > + dv_reg DDRPHYID_REV; > + dv_reg SDSRETR; > + dv_reg EIRR; > + dv_reg EIMR; > + dv_reg EIMSR; > + dv_reg EIMCR; > + dv_reg IOCTRLR; > + dv_reg IOSTATR; > + u_int8_t RSVD0[8]; > + dv_reg NANDFCR; > + dv_reg NANDFSR; > + u_int8_t RSVD1[8]; > + dv_reg NANDF1ECC; > + dv_reg NANDF2ECC; > + dv_reg NANDF3ECC; > + dv_reg NANDF4ECC; > + u_int8_t RSVD2[60]; > + dv_reg NAND4BITECCLOAD; > + dv_reg NAND4BITECC1; > + dv_reg NAND4BITECC2; > + dv_reg NAND4BITECC3; > + dv_reg NAND4BITECC4; > + dv_reg NANDERRADD1; > + dv_reg NANDERRADD2; > + dv_reg NANDERRVAL1; > + dv_reg NANDERRVAL2; > +} emif_registers; > + > +typedef emif_registers *emifregs; > +#endif > diff --git a/include/asm-arm/arch-da8xx/hardware.h > b/include/asm-arm/arch-da8xx/hardware.h > new file mode 100644 > index 0000000..7cfe8d2 > --- /dev/null > +++ b/include/asm-arm/arch-da8xx/hardware.h > @@ -0,0 +1,221 @@ > +/* I believe this could be combined with davinci. There is already logic in davinci hardware.h to handle SOC specific memory maps. > + * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc > + * > + * Based on hardware.h for DaVinci. Original Copyrights follow. > + * > + * Sergey Kubushyn <[email protected]> > + * Copyright (C) 2007 Sergey Kubushyn <[email protected]> > + * > + * Based on: > + * > + * ------------------------------------------------------------------------- > + * > + * linux/include/asm-arm/arch-davinci/hardware.h > + * > + * Copyright (C) 2006 Texas Instruments. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + */ > +#ifndef __DA8XX_HARDWARE_H > +#define __DA8XX_HARDWARE_H > + > +#include <config.h> > + > +#ifndef __ASSEMBLY__ > + > +#include <asm/sizes.h> > + > +/* required by davinci drivers */ > +#define REG(addr) (*(volatile unsigned int *)(addr)) Thank you for the comment. Yes it is.. The direct access should be cleaned up to writel/readl. You get a pass on this. > + > +/* required by davinci drivers */ > +typedef volatile unsigned int dv_reg; > +typedef volatile unsigned int *dv_reg_p; > + > +#endif > + > +/* > + * Base register addresses > + */ > +#define DAVINCI_UART0_BASE 0x01c42000 > +#define DAVINCI_UART1_BASE 0x01d0c000 > +#define DAVINCI_UART2_BASE 0x01d0d000 > +#define DAVINCI_I2C0_BASE 0x01c22000 > +#define DAVINCI_I2C1_BASE 0x01e28000 > +#define DAVINCI_TIMER0_BASE 0x01c20000 > +#define DAVINCI_TIMER1_BASE 0x01c21000 > +#define DAVINCI_WDOG_BASE 0x01c21000 > +#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000 > +#define DAVINCI_PSC0_BASE 0x01c10000 > +#define DAVINCI_PSC1_BASE 0x01e27000 > +#define DAVINCI_SPI0_BASE 0x01c41000 > +#define DAVINCI_USB_OTG_BASE 0x01e00000 > +#define DAVINCI_SPI1_BASE 0x01e12000 > +#define DAVINCI_GPIO_BASE 0x01e26000 > +#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 > +#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 > +#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000 > +#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000 > +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000 > +#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000 > +#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000 > +#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000 > +#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000 > +#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000 > +#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000 > +#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 > +#define DAVINCI_INTC_BASE 0xfffee000 > +#define DAVINCI_BOOTCFG_BASE 0x01c14000 > + > +/* Clock IDs */ > +#define DAVINCI_PLLM_CLKID (0xFF + 0) > +#define DAVINCI_PLLC_CLKID (0xFF + 1) > +#define DAVINCI_AUXCLK_CLKID (0xFF + 2) > +#define DAVINCI_MDIO_CLKID 4 > +#define DAVINCI_SPI0_CLKID 2 > +#define DAVINCI_UART2_CLKID 2 > +#define DAVINCI_ARM_CLKID 6 > + > +/* Power and Sleep Controller (PSC) Domains */ > +#define DAVINCI_GPSC_ARMDOMAIN 0 > +#define DAVINCI_GPSC_DSPDOMAIN 1 > + > +/* LPSCs in PSC0 */ > +#define DAVINCI_LPSC_TPCC 0 > +#define DAVINCI_LPSC_TPTC0 1 > +#define DAVINCI_LPSC_TPTC1 2 > +#define DAVINCI_LPSC_AEMIF 3 > +#define DAVINCI_LPSC_SPI0 4 > +#define DAVINCI_LPSC_MMC_SD 5 > +#define DAVINCI_LPSC_AINTC 6 > +#define DAVINCI_LPSC_ARM_RAM_ROM 7 > +#define DAVINCI_LPSC_SECCTL_KEYMGR 8 > +#define DAVINCI_LPSC_UART0 9 > +#define DAVINCI_LPSC_SCR0 10 > +#define DAVINCI_LPSC_SCR1 11 > +#define DAVINCI_LPSC_SCR2 12 > +#define DAVINCI_LPSC_DMAX 13 > +#define DAVINCI_LPSC_ARM 14 > +#define DAVINCI_LPSC_GEM 15 > + > +/* for LPSCs in PSC1, 32 + actual id is being used for differentiation */ > +#define DAVINCI_LPSC_BASE 32 > +#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_BASE + 1) > +#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_BASE + 2) > +#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_BASE + 3) > +#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_BASE + 4) > +#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_BASE + 5) > +#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_BASE + 6) > +#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_BASE + 7) > +#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_BASE + 8) > +#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_BASE + 9) > +#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_BASE + 10) > +#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_BASE + 11) > +#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_BASE + 12) > +#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_BASE + 13) > +#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_BASE + 16) > +#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_BASE + 17) > +#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_BASE + 20) > +#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_BASE + 21) > +#define DAVINCI_LPSC_SCR_P0 (DAVINCI_LPSC_BASE + 22) > +#define DAVINCI_LPSC_SCR_P1 (DAVINCI_LPSC_BASE + 23) > +#define DAVINCI_LPSC_CR_P3 (DAVINCI_LPSC_BASE + 26) > +#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_BASE + 31) > + > +/* Some PSC defines */ > + > +#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) > +#define PSC0_MDSTAT (DAVINCI_PSC0_BASE + 0x800) > +#define PSC0_PTCMD (DAVINCI_PSC0_BASE + 0x120) > +#define PSC0_PTSTAT (DAVINCI_PSC0_BASE + 0x128) > + > +#define PSC1_MDCTL (DAVINCI_PSC1_BASE + 0xa00) > +#define PSC1_MDSTAT (DAVINCI_PSC1_BASE + 0x800) > +#define PSC1_PTCMD (DAVINCI_PSC1_BASE + 0x120) > +#define PSC1_PTSTAT (DAVINCI_PSC1_BASE + 0x128) > + > +/* Some PLL defines */ > +#define PLL0_PLLCTL (DAVINCI_PLL_CNTRL0_BASE + 0x100) > +#define PLL0_PLLM (DAVINCI_PLL_CNTRL0_BASE + 0x110) > +#define PLL0_PREDIV (DAVINCI_PLL_CNTRL0_BASE + 0x114) > +#define PLL0_POSTDIV (DAVINCI_PLL_CNTRL0_BASE + 0x128) > +#define PLL0_DIV1 (DAVINCI_PLL_CNTRL0_BASE + 0x118) > +#define PLL0_DIV2 (DAVINCI_PLL_CNTRL0_BASE + 0x11c) > +#define PLL0_DIV3 (DAVINCI_PLL_CNTRL0_BASE + 0x120) > +#define PLL0_DIV4 (DAVINCI_PLL_CNTRL0_BASE + 0x160) > +#define PLL0_DIV5 (DAVINCI_PLL_CNTRL0_BASE + 0x164) > +#define PLL0_DIV6 (DAVINCI_PLL_CNTRL0_BASE + 0x168) > +#define PLL0_DIV7 (DAVINCI_PLL_CNTRL0_BASE + 0x16c) > +#define PLL0_DIV8 (DAVINCI_PLL_CNTRL0_BASE + 0x170) > +#define PLL0_DIV9 (DAVINCI_PLL_CNTRL0_BASE + 0x114) > + > +/* Boot config */ > +#define PINMUX0 (DAVINCI_BOOTCFG_BASE + 0x120) > +#define PINMUX1 (DAVINCI_BOOTCFG_BASE + 0x124) > +#define PINMUX2 (DAVINCI_BOOTCFG_BASE + 0x128) > +#define PINMUX3 (DAVINCI_BOOTCFG_BASE + 0x12c) > +#define PINMUX4 (DAVINCI_BOOTCFG_BASE + 0x130) > +#define PINMUX5 (DAVINCI_BOOTCFG_BASE + 0x134) > +#define PINMUX6 (DAVINCI_BOOTCFG_BASE + 0x138) > +#define PINMUX7 (DAVINCI_BOOTCFG_BASE + 0x13c) > +#define PINMUX8 (DAVINCI_BOOTCFG_BASE + 0x140) > +#define PINMUX9 (DAVINCI_BOOTCFG_BASE + 0x144) > +#define PINMUX10 (DAVINCI_BOOTCFG_BASE + 0x148) > +#define PINMUX11 (DAVINCI_BOOTCFG_BASE + 0x14c) > +#define PINMUX12 (DAVINCI_BOOTCFG_BASE + 0x150) > +#define PINMUX13 (DAVINCI_BOOTCFG_BASE + 0x154) > +#define PINMUX14 (DAVINCI_BOOTCFG_BASE + 0x158) > +#define PINMUX15 (DAVINCI_BOOTCFG_BASE + 0x15C) > +#define PINMUX16 (DAVINCI_BOOTCFG_BASE + 0x160) > +#define PINMUX17 (DAVINCI_BOOTCFG_BASE + 0x164) > +#define PINMUX18 (DAVINCI_BOOTCFG_BASE + 0x168) > +#define PINMUX19 (DAVINCI_BOOTCFG_BASE + 0x16c) > +#define SUSPSRC (DAVINCI_BOOTCFG_BASE + 0x170) > +#define CFGCHIP0 (DAVINCI_BOOTCFG_BASE + 0x17c) > +#define CFGCHIP2 (DAVINCI_BOOTCFG_BASE + 0x184) > + > +/* Interrupt controller */ > +#define INTC_GLB_EN (DAVINCI_INTC_BASE + 0x10) > +#define INTC_HINT_EN (DAVINCI_INTC_BASE + 0x1500) > +#define INTC_EN_CLR0 (DAVINCI_INTC_BASE + 0x380) > + > +/* GPIO */ > +#define GPIO_BANK4_ADDR 0x01E26000 > +#define GPIO_BANK4_REG_DIR_ADDR (GPIO_BANK4_ADDR + 0x60) > +#define GPIO_BANK4_REG_OPDATA_ADDR (GPIO_BANK4_ADDR + 0x64) > +#define GPIO_BANK4_REG_SET_ADDR (GPIO_BANK4_ADDR + 0x68) > +#define GPIO_BANK4_REG_CLR_ADDR (GPIO_BANK4_ADDR + 0x6C) > + > +/* Emulation suspend bits */ > +#define SUSPSRC_EMAC (1 << 5) > +#define SUSPSRC_I2C (1 << 16) > +#define SUSPSRC_SPI0 (1 << 21) > +#define SUSPSRC_UART2 (1 << 20) > +#define SUSPSRC_TIMER0 (1 << 27) > + > +/* UART PWREMU_MGMT definitions */ > +#define PWREMU_MGMT_BASE (0x30) > +#define PWREMU_MGMT_FREE (1 << 0) > +#define PWREMU_MGMT_URRST (1 << 13) > +#define PWREMU_MGMT_UTRST (1 << 14) > + > +#endif /* __DA8XX_HARDWARE_H */ > diff --git a/include/asm-arm/arch-da8xx/i2c_defs.h > b/include/asm-arm/arch-da8xx/i2c_defs.h > new file mode 100644 > index 0000000..df4676a > --- /dev/null > +++ b/include/asm-arm/arch-da8xx/i2c_defs.h > @@ -0,0 +1,93 @@ > +/* > + * (C) Copyright 2004 > + * Texas Instruments, <www.ti.com> > + * > + * Some changes copyright (C) 2007 Sergey Kubushyn <[email protected]> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > +#ifndef _DAVINCI_I2C_H_ > +#define _DAVINCI_I2C_H_ > + > +#define I2C_WRITE 0 > +#define I2C_READ 1 > + > +#define I2C_BASE 0x01c22000 This is the only difference I could find between this and the davinci version. This could be easily combined. > + > +#define I2C_OA (I2C_BASE + 0x00) > +#define I2C_IE (I2C_BASE + 0x04) > +#define I2C_STAT (I2C_BASE + 0x08) > +#define I2C_SCLL (I2C_BASE + 0x0c) > +#define I2C_SCLH (I2C_BASE + 0x10) > +#define I2C_CNT (I2C_BASE + 0x14) > +#define I2C_DRR (I2C_BASE + 0x18) > +#define I2C_SA (I2C_BASE + 0x1c) > +#define I2C_DXR (I2C_BASE + 0x20) > +#define I2C_CON (I2C_BASE + 0x24) > +#define I2C_IV (I2C_BASE + 0x28) > +#define I2C_PSC (I2C_BASE + 0x30) > + > +/* I2C masks */ > + > +/* I2C Interrupt Enable Register (I2C_IE): */ > +#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt > enable */ > +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt > enable */ > +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable > */ > +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt > enable */ > +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable > */ > +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ > + > +/* I2C Status Register (I2C_STAT): */ > + > +#define I2C_STAT_BB (1 << 12) /* Bus busy */ > +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ > +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ > +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ > +#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */ > +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ > +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ > +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ > +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable > */ > +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ > + > +/* I2C Interrupt Code Register (I2C_INTCODE): */ > + > +#define I2C_INTCODE_MASK 7 > +#define I2C_INTCODE_NONE 0 > +#define I2C_INTCODE_AL 1 /* Arbitration lost */ > +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ > +#define I2C_INTCODE_ARDY 3 /* Register access ready */ > +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ > +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ > +#define I2C_INTCODE_SCD 6 /* Stop condition detect */ > + > +/* I2C Configuration Register (I2C_CON): */ > + > +#define I2C_CON_EN (1 << 5) /* I2C module enable */ > +#define I2C_CON_STB (1 << 4) /* Start byte mode (master only) */ > +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ > +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master only) */ > +#define I2C_CON_XA (1 << 8) /* Expand address */ > +#define I2C_CON_STP (1 << 11) /* Stop condition (master only) */ > +#define I2C_CON_STT (1 << 13) /* Start condition (master only) */ > +#define I2C_CON_FREE (1 << 14) /* Free run on emulation */ > + > +#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */ > + > +#endif > _______________________________________________ > U-Boot mailing list > [email protected] > http://lists.denx.de/mailman/listinfo/u-boot _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
