On 02/15/2017 07:07 AM, Ashish Kumar wrote: > The QorIQ LS1088A processor is built on the Layerscape > architecture combining eight ARM A53 processor cores > with advanced, high-performance datapath acceleration > and networks, peripheral interfaces required for > networking, wireless infrastructure, and general-purpose > embedded applications. > > LS1088A is compliant to the Layerscape Chassis Generation 3. > > Features summary: > - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs > - Cores are in 2 cluster of 4-cores each > - Cache coherent interconnect (CCI-400) > - One 64-bit DDR4 SDRAM memory controller with ECC > - Data path acceleration architecture 2.0 (DPAA2) > - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs > - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc >
Please remove the indentation in commit message. > Signed-off-by: Alison Wang <[email protected]> > Signed-off-by: Prabhakar Kushwaha <[email protected]> > Signed-off-by: Ashish Kumar <[email protected]> > --- > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 + > .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 10 ++ > arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 124 > +++++++++++++++++++++ > arch/arm/include/asm/arch-fsl-layerscape/config.h | 46 ++++++++ > arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 + > .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 + > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 11 ++ > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 4 + > drivers/net/ldpaa_eth/Makefile | 1 + > drivers/net/ldpaa_eth/ls1088a.c | 87 +++++++++++++++ > 10 files changed, 292 insertions(+) > create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c > create mode 100644 drivers/net/ldpaa_eth/ls1088a.c > <snip> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > index 83f5501..3aed123 100644 > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > @@ -219,6 +219,52 @@ > > #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 > > +#elif defined(CONFIG_ARCH_LS1088A) > +#define CONFIG_MAX_CPUS 8 > +#define CONFIG_SYS_FSL_NUM_CC_PLLS 3 > +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 > +#define CONFIG_NUM_DDR_CONTROLLERS 1 > +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } > +#define CONFIG_SYS_FSL_PLATFORM_CLK_RATIO 1 > +#define CONFIG_GICV3 > +#define CONFIG_FSL_TZPC_BP147 > +#define CONFIG_FSL_TZASC_400 > +#define CONFIG_FSL_TZASC_1 > + > +#define SRDS_MAX_LANES 4 > +#define CONFIG_SYS_FSL_SRDS_1 > +#define CONFIG_SYS_FSL_SRDS_2 > + > +/* DDR */ > +#define CONFIG_SYS_FSL_DDR_LE > +#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) > +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE > + > +#define CONFIG_SYS_FSL_CCSR_GUR_LE > +#define CONFIG_SYS_FSL_CCSR_SCFG_LE > +#define CONFIG_SYS_FSL_ESDHC_LE > +#define CONFIG_SYS_FSL_IFC_LE > +#define CONFIG_SYS_FSL_PEX_LUT_LE > + > +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN > + > +/* SFP */ > +#define CONFIG_SYS_FSL_SFP_VER_3_4 > +#define CONFIG_SYS_FSL_SFP_LE > +#define CONFIG_SYS_FSL_SRK_LE > + > +/* SEC */ > +#define CONFIG_SYS_FSL_SEC_LE > +#define CONFIG_SYS_FSL_SEC_COMPAT 5 > + > +/* Security Monitor */ > +#define CONFIG_SYS_FSL_SEC_MON_LE > + > +/* Secure Boot */ > +#define CONFIG_ESBC_HDR_LS > + > +/* DCFG - GUR */ > +#define CONFIG_SYS_FSL_CCSR_GUR_LE > #else > #error SoC not defined > #endif Many of your config macros were moved into Kconfig. You made the update in your #2 and #3 patches. How did you miss this one? Please update your patch. York _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
