Hi Stefano, > -----Original Message----- > From: Stefano Babic [mailto:[email protected]] > Sent: Thursday, April 13, 2017 12:45 AM > To: Peng Fan <[email protected]>; [email protected] > Cc: [email protected]; [email protected]; [email protected] > Subject: Re: [PATCH 1/2] imx-common: Enable ACTLR.SMP bit for i.MX cortex- > a7 platforms > > Hi Peng, > > On 05/04/2017 04:36, Peng Fan wrote: > > According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure > > this bit is set to 1 before the caches and MMU are enabled, or any > > cache and TLB maintenance operations are performed". > > > > True, understood, thanks. > > > ROM sets this bit in normal boot flow, but when in serial download > > mode, it is not set. Here we add it in u-boot as a common flow for all > > i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. > > > > When cache not enabled in U-Boot, we also need enable the SMP bit. > > because kernel does not set this bit, if this bit not enabled, kernel > > works as cache disabled. > > > > Anyway, it looks to me wrong to fix this in i.MX code, as this must be fixed > for > all Cortex-A7. It should be fixed in general ARM code. > > And Andre has already sent patches for this (at least for sunxi), but with the > opposite rule (default is set if not specific requested).
Thanks for correcting me. I see Andre's patch https://lists.denx.de/pipermail/u-boot/2017-February/279918.html It only handles sunxi platform. If we need fix i.MX A7 cores, do you prefer I set the SMP bit in s_init for i.MX6UL/7? Or you prefer this should be handled by common ARM code? I do not see code the detect A7/A9 in U-Boot now. Thanks, Peng. > > Regards, > Stefano > > > Signed-off-by: Peng Fan <[email protected]> > > Signed-off-by: Ye Li <[email protected]> > > Cc: Stefano Babic <[email protected]> > > --- > > arch/arm/cpu/armv7/mx7/soc.c | 7 ------- > > arch/arm/imx-common/cache.c | 42 > > ++++++++++++++++++++++++++++++++++++++++++ > > 2 files changed, 42 insertions(+), 7 deletions(-) > > > > diff --git a/arch/arm/cpu/armv7/mx7/soc.c > > b/arch/arm/cpu/armv7/mx7/soc.c index 8422f24..b847cf8 100644 > > --- a/arch/arm/cpu/armv7/mx7/soc.c > > +++ b/arch/arm/cpu/armv7/mx7/soc.c > > @@ -446,13 +446,6 @@ int mmc_get_env_dev(void) > > > > void s_init(void) > > { > > -#if !defined CONFIG_SPL_BUILD > > - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ > > - asm volatile( > > - "mrc p15, 0, r0, c1, c0, 1\n" > > - "orr r0, r0, #1 << 6\n" > > - "mcr p15, 0, r0, c1, c0, 1\n"); > > -#endif > > /* clock configuration. */ > > clock_init(); > > > > diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c > > index 1c4a9a2..ed17f9e 100644 > > --- a/arch/arm/imx-common/cache.c > > +++ b/arch/arm/imx-common/cache.c > > @@ -10,6 +10,34 @@ > > #include <asm/io.h> > > #include <asm/imx-common/sys_proto.h> > > > > +static void enable_ca7_smp(void) > > +{ > > + uint32_t val; > > + > > + /* Read MIDR */ > > + asm volatile ("mrc p15, 0, %0, c0, c0, 0\r\n" : "=r"(val)); > > + val = (val >> 4); > > + val &= 0xfff; > > + > > + /* Only set the SMP for Cortex A7 */ > > + if (val == 0xC07) { > > + /* Read auxiliary control register */ > > + asm volatile ("mrc p15, 0, %0, c1, c0, 1\r\n" : "=r"(val)); > > + > > + if (val & (1 << 6)) > > + return; > > + > > + /* Enable SMP */ > > + val |= (1 << 6); > > + > > + /* Write auxiliary control register */ > > + asm volatile ("mcr p15, 0, %0, c1, c0, 1\r\n" : : "r"(val)); > > + > > + DSB; > > + ISB; > > + } > > +} > > + > > #ifndef CONFIG_SYS_DCACHE_OFF > > void enable_caches(void) > > { > > @@ -18,6 +46,9 @@ void enable_caches(void) #else > > enum dcache_option option = DCACHE_WRITEBACK; #endif > > + /* Set ACTLR.SMP bit for Cortex-A7 */ > > + enable_ca7_smp(); > > + > > /* Avoid random hang when download by usb */ > > invalidate_dcache_all(); > > > > @@ -32,6 +63,17 @@ void enable_caches(void) > > IRAM_SIZE, > > option); > > } > > +#else > > +void enable_caches(void) > > +{ > > + /* > > + * Set ACTLR.SMP bit for Cortex-A7, even the > > + * caches not enabled. > > + */ > > + enable_ca7_smp(); > > + > > + puts("WARNING: Caches not enabled\n"); } > > #endif > > > > #ifndef CONFIG_SYS_L2CACHE_OFF > > > > > -- > ============================================================ > ========= > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: [email protected] > ============================================================ > ========= _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
