From: Suresh Gupta <suresh.gu...@freescale.com>
USB3 LFPS Peak-Peak Differential Output Voltage Adjustment
This patch is adding the erratum for LS1043 and LS2080 SoCs.
Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 29 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 +++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
3 files changed, 35 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 27eb8fb..c42d778 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -47,6 +47,33 @@ static void erratum_a009798(void)
#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
}
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+ val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+ val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+ u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+ u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+ val &= ~(0x7F << 9);
+ scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+ val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -221,6 +248,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+ erratum_a008997();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -493,6 +521,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009798();
+ erratum_a008997();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5763586..554def5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -198,8 +198,12 @@ struct ccsr_gur {
#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
+#define SCFG_BASE 0x01570000
+#define SCFG_USB3PRM1CR_USB1 0x070
+#define SCFG_USB3PRM2CR_USB1 0x074
#define SCFG_USB3PRM1CR_USB2 0x07C
#define SCFG_USB3PRM1CR_USB3 0x088
+#define SCFG_USB3PRM2CR_USB3 0x08c
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 281f0ee..b428b18 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -129,9 +129,11 @@
/* Supplemental Configuration */
#define SCFG_BASE 0x01fc0000
#define SCFG_USB3PRM1CR 0x000
+#define SCFG_USB3PRM2CR 0x004
#define SCFG_USB3PRM1CR_INIT 0x27672b2a
#define USB_TXVREFTUNE 0x9
#define USB_SQRXTUNE 0xFC7FFFFF
+#define USB_PCSTXSWINGFULL 0x47
#define SCFG_QSPICLKCTLR 0x10
#define TP_ITYP_AV 0x00000001 /* Initiator available */
--
2.1.0.27.g96db324
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