于 2017年5月10日 GMT+08:00 上午7:44:21, "André Przywara" <[email protected]> 写到: >On 26/04/17 15:50, Icenowy Zheng wrote: >> From: Icenowy Zheng <[email protected]> >> >> As we added LPDDR3 support in the former patch, we need a set of >timing >> info to really enable it. >> >> Add the timing info used by stock boot0. > >When I checked the disassembly/decompile for the Pine64 libdram, I >found >some more registers differing when DRAM type is 7 (LPDDR3), mostly in >mctl_channel_init(). I can send patches on top of this series to set >those bits. >Does it work reliably for you with this series?
Yes, tested on a SoPine w/ baseboard and a Pinebook. > >More below ... > >> Signed-off-by: Icenowy Zheng <[email protected]> >> --- >> arch/arm/mach-sunxi/dram_timings/Makefile | 1 + >> arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c | 84 >+++++++++++++++++++++++++ >> board/sunxi/Kconfig | 7 +++ >> 3 files changed, 92 insertions(+) >> create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c >> >> diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile >b/arch/arm/mach-sunxi/dram_timings/Makefile >> index a4c9dc556c..278a8a14cc 100644 >> --- a/arch/arm/mach-sunxi/dram_timings/Makefile >> +++ b/arch/arm/mach-sunxi/dram_timings/Makefile >> @@ -1,2 +1,3 @@ >> obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o >> +obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o >> obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o >> diff --git a/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c >b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c >> new file mode 100644 >> index 0000000000..1085efe48e >> --- /dev/null >> +++ b/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c >> @@ -0,0 +1,84 @@ >> +#include <common.h> >> +#include <asm/arch/dram.h> >> +#include <asm/arch/cpu.h> >> + >> +void mctl_set_timing_params(uint16_t socid, struct dram_para *para) >> +{ >> + struct sunxi_mctl_ctl_reg * const mctl_ctl = >> + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; >> + >> + u8 tccd = 2; >> + u8 tfaw = max(ns_to_t(50), 4); >> + u8 trrd = max(ns_to_t(10), 2); >> + u8 trcd = max(ns_to_t(24), 2); >> + u8 trc = ns_to_t(70); >> + u8 txp = max(ns_to_t(8), 2); >> + u8 twtr = max(ns_to_t(8), 2); >> + u8 trtp = max(ns_to_t(8), 2); >> + u8 twr = max(ns_to_t(15), 3); >> + u8 trp = max(ns_to_t(27), 2); >> + u8 tras = ns_to_t(42); >> + u16 trefi = ns_to_t(3900) / 32; >> + u16 trfc = ns_to_t(210); > >Where do those values come from? > >> + >> + u8 tmrw = 5; >> + u8 tmrd = 5; >> + u8 tmod = 12; >> + u8 tcke = 3; >> + u8 tcksrx = 5; >> + u8 tcksre = 5; >> + u8 tckesr = 5; >> + u8 trasmax = 24; >> + >> + u8 tcl = 6; /* CL 12 */ >> + u8 tcwl = 3; /* CWL 6 */ >> + u8 t_rdata_en = 5; >> + u8 wr_latency = 2; >> + >> + u32 tdinit0 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ >> + u32 tdinit1 = (100 * CONFIG_DRAM_CLK) / 1000 + 1; /* 100ns */ >> + u32 tdinit2 = (11 * CONFIG_DRAM_CLK) + 1; /* 11us */ >> + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ >> + >> + u8 twtp = tcwl + 4 + twr + 1; >> + u8 twr2rd = tcwl + 4 + 1 + twtr; >> + u8 trd2wr = tcl + 4 + 5 - tcwl + 1; >> + >> + /* set mode register */ > >I found explanations for the mode registers in the datasheet for the >PineBook DRAM, so: > >> + writel(0, &mctl_ctl->mr[0]); > >According to the datasheet (and generic LPDDR3 docs) this register is >read-only, so we don't need to write this at all. > >> + writel(0xc3, &mctl_ctl->mr[1]); > >Can you add: /* nWR=8, BL8 */ to document the magic value? > >> + writel(0xa, &mctl_ctl->mr[2]); /* CWL=6 */ > >Can you change this comment to: /* RL=12, WL=6 */ ? >Also according to the datasheet for 533 MHz we can go with RL=8 and >WL=4, which would encode as "0x6". Maybe worth experimenting with, or >adding as a TODO. > >> + writel(0x2, &mctl_ctl->mr[3]); > >Can you add: /* 40 Ohms PD/PU */ ? > >> + >> + /* set DRAM timing */ >> + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | >> + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), >> + &mctl_ctl->dramtmg[0]); >> + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), >> + &mctl_ctl->dramtmg[1]); >> + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | >> + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), >> + &mctl_ctl->dramtmg[2]); >> + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | >DRAMTMG3_TMOD(tmod), >> + &mctl_ctl->dramtmg[3]); >> + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | >DRAMTMG4_TRRD(trrd) | >> + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); >> + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | >> + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), >> + &mctl_ctl->dramtmg[5]); > >As this block is the same as for DDR3, I wonder if it's worth factoring >this out. But this may be part of a future rework. > >Cheers, >Andre > >> + >> + /* set two rank timing */ >> + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), >> + (0x66 << 8) | (0x10 << 0)); >> + >> + /* set PHY interface timing, write latency and read latency >configure */ >> + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | >> + (wr_latency << 0), &mctl_ctl->pitmg[0]); >> + >> + /* set PHY timing, PTR0-2 use default */ >> + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), >&mctl_ctl->ptr[3]); >> + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), >&mctl_ctl->ptr[4]); >> + >> + /* set refresh timing */ >> + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), >&mctl_ctl->rfshtmg); >> +} >> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig >> index 8be75048d1..7ad00bb162 100644 >> --- a/board/sunxi/Kconfig >> +++ b/board/sunxi/Kconfig >> @@ -262,6 +262,13 @@ config SUNXI_DRAM_DDR3_1333 >> This option is the original only supported memory type, which suits >> many H3/H5/A64 boards available now. >> >> +config SUNXI_DRAM_LPDDR3_STOCK >> + bool "LPDDR3 with Allwinner stock configuration" >> + select SUNXI_DRAM_LPDDR3 >> + ---help--- >> + This option is the LPDDR3 timing used by the stock boot0 by >> + Allwinner. >> + >> config SUNXI_DRAM_DDR2_V3S >> bool "DDR2 found in V3s chip" >> select SUNXI_DRAM_DDR2 >> _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
