This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas <nolt...@gmail.com>
---
arch/mips/dts/brcm,bcm6338.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6338.dtsi b/arch/mips/dts/brcm,bcm6338.dtsi
index eb51a43..614792e 100644
--- a/arch/mips/dts/brcm,bcm6338.dtsi
+++ b/arch/mips/dts/brcm,bcm6338.dtsi
@@ -109,6 +109,19 @@
status = "disabled";
};
+ spi: spi@fffe0c00 {
+ compatible = "brcm,bcm6338-spi";
+ reg = <0xfffe0c00 0xc0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&periph_clk BCM6338_CLK_SPI>;
+ resets = <&periph_rst BCM6338_RST_SPI>;
+ spi-max-frequency = <20000000>;
+ num-cs = <4>;
+
+ status = "disabled";
+ };
+
memory-controller@fffe3100 {
compatible = "brcm,bcm6338-mc";
reg = <0xfffe3100 0x38>;
--
2.1.4
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