On 03/05/2017 11:59, Benoît Thébaudeau wrote: > The maximum SD clock frequency in High Speed mode is 50 MHz. This change > makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1) > instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2). > > Signed-off-by: Benoît Thébaudeau <ben...@wsystem.com> > --- > board/freescale/mx25pdk/mx25pdk.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/board/freescale/mx25pdk/mx25pdk.c > b/board/freescale/mx25pdk/mx25pdk.c > index 788d3c3..cab769c 100644 > --- a/board/freescale/mx25pdk/mx25pdk.c > +++ b/board/freescale/mx25pdk/mx25pdk.c > @@ -175,6 +175,12 @@ int board_mmc_init(bd_t *bis) > > imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); > > + /* > + * Set the eSDHC1 PER clock to the maximum frequency lower than or equal > + * to 50 MHz that can be obtained, which requires to use UPLL as the > + * clock source. This actually gives 48 MHz. > + */ > + imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000); > esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); > return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); > } >
Applied to u-boot-imx -master, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de ===================================================================== _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
