> On 23 Jun 2017, at 10:49, Kever Yang <[email protected]> wrote: > > Hi Philipp, > > > On 06/12/2017 07:00 PM, Philipp Tomsich wrote: >> >> >> On Fri, 9 Jun 2017, Kever Yang wrote: >> >>> Add clock driver init support for: >>> - cpu, bus clock init; >>> - emmc, sdmmc clock; >>> - ddr clock; >>> >>> Signed-off-by: Kever Yang <[email protected]> >>> --- >>> >>> arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 ++++++++++++ >>> drivers/clk/rockchip/Makefile | 1 + >>> drivers/clk/rockchip/clk_rk322x.c | 413 >>> ++++++++++++++++++++++++ >>> 3 files changed, 629 insertions(+) >>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h >>> create mode 100644 drivers/clk/rockchip/clk_rk322x.c >>> >>> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h >>> b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h >>> new file mode 100644 >>> index 0000000..0a01f87 >>> --- /dev/null >>> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h >>> @@ -0,0 +1,215 @@ >>> +/* >>> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd >>> + * >>> + * SPDX-License-Identifier: GPL-2.0+ >>> + */ >>> +#ifndef _ASM_ARCH_CRU_RK322X_H >>> +#define _ASM_ARCH_CRU_RK322X_H >>> + >>> +#include <common.h> >>> + >>> +#define MHz 1000000 >>> +#define OSC_HZ (24 * MHz) >>> + >>> +#define APLL_HZ (600 * MHz) >>> +#define GPLL_HZ (594 * MHz) >>> + >>> +#define CORE_PERI_HZ 150000000 >>> +#define CORE_ACLK_HZ 300000000 >>> + >>> +#define BUS_ACLK_HZ 148500000 >>> +#define BUS_HCLK_HZ 148500000 >>> +#define BUS_PCLK_HZ 74250000 >>> + >>> +#define PERI_ACLK_HZ 148500000 >>> +#define PERI_HCLK_HZ 148500000 >>> +#define PERI_PCLK_HZ 74250000 >>> + >>> +/* Private data for the clock driver - used by rockchip_get_cru() */ >>> +struct rk322x_clk_priv { >>> + struct rk322x_cru *cru; >>> + ulong rate; >>> +}; >>> + >>> +struct rk322x_cru { >>> + struct rk322x_pll { >>> + unsigned int con0; >>> + unsigned int con1; >>> + unsigned int con2; >>> + } pll[4]; >>> + unsigned int reserved0[4]; >>> + unsigned int cru_mode_con; >>> + unsigned int cru_clksel_con[35]; >>> + unsigned int cru_clkgate_con[16]; >>> + unsigned int cru_softrst_con[9]; >>> + unsigned int cru_misc_con; >>> + unsigned int reserved1[2]; >>> + unsigned int cru_glb_cnt_th; >>> + unsigned int reserved2[3]; >>> + unsigned int cru_glb_rst_st; >>> + unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1]; >> >> It took me a moment to understand why the 'minus one'. >> >> Could you introduce a macro for this along the lines of >> U32_ELEMS_START_TO_LAST(0x1c0, 0x14c) >> or something similar... I fail to come up with a concise >> name that clearly says "from 0x1c0 and covering up to, >> but excluding, the address 0x150"). > > Well, I will keep it as-is for this patch set, because this is widely used > for all other Rockchip SoCs, if we need to do this, we'd better > have a clean for all of them.
Ok. I’ll apply as is. _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
