Sometimes the EPHY clock macros are not defined for non-H3/H5 platforms (e.g. A83T), which makes the driver to fail to be built.
Only build the EPHY clock code when the SoC is H3/H5 by wrap them into an #ifdef. Signed-off-by: Icenowy Zheng <[email protected]> --- drivers/net/sun8i_emac.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 09bbb2cdb5..c071f5d3c3 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -604,6 +604,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#if defined(CONFIG_MACH_SUNXI_H3_H5) if (priv->use_internal_phy) { /* Set clock gating for ephy */ setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); @@ -611,6 +612,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) /* Deassert EPHY */ setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); } +#endif /* Set clock gating for emac */ setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); -- 2.13.0 _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
