Rx Compliance tests may fail intermittently at high jitter frequencies using default register values.
Changes identified in setup makes the Rx compliance test pass. Signed-off-by: Sriram Dash <[email protected]> Signed-off-by: Rajesh Bhagat <[email protected]> Signed-off-by: Suresh Gupta <[email protected]> Signed-off-by: Ran Wang <[email protected]> --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 ++++- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 55 ++++++++++++++++++++++ .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 ++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 ++++ 4 files changed, 83 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 867794d..3f63694 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -25,6 +25,7 @@ config ARCH_LS1043A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R @@ -48,6 +49,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -86,6 +88,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A008997 + select SYS_FSL_ERRATUM_A009007 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F @@ -236,7 +239,14 @@ config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798" config SYS_FSL_ERRATUM_A008997 - bool "Workaround for USB PHY erratum A008997" + bool + help + Workaround for USB PHY erratum A008997 + +config SYS_FSL_ERRATUM_A009007 + bool + help + Workaround for USB PHY erratum A009007 config MAX_CPUS int "Maximum number of CPUs permitted for Layerscape" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7ebb8d4..5810f42 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -115,6 +115,59 @@ static void erratum_a008997(void) #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } +static void erratum_a009007(void) +{ +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + void __iomem *usb_phy = (void __iomem *)USB_PHY1; + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); + + usb_phy = (void __iomem *)USB_PHY2; + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); + + usb_phy = (void __iomem *)USB_PHY3; + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_be16(usb_phy + USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); +#elif defined(CONFIG_ARCH_LS2080A) + void __iomem *dcsr = (void __iomem *)DCSR_BASE; + out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_le16(dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); + out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_1); + out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_2); + out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_3); + out_le16(dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI, + USB_PHY_RX_EQ_VAL_4); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */ +} + #if defined(CONFIG_FSL_LSCH3) /* * This erratum requires setting a value to eddrtqcr1 to @@ -264,6 +317,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -542,6 +596,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009008(); erratum_a009798(); erratum_a008997(); + erratum_a009007(); } #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 2e52078..69fd79c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -347,6 +347,14 @@ struct ccsr_gur { #define USB_TXVREFTUNE 0x9 #define USB_SQRXTUNE 0xFC7FFFFF #define USB_PCSTXSWINGFULL 0x47 +#define USB_PHY1 0x084F0000 +#define USB_PHY2 0x08500000 +#define USB_PHY3 0x08510000 +#define USB_PHY_RX_OVRD_IN_HI 0x200c +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80 #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 2d309d5..238d647 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -137,6 +137,15 @@ #define USB_SQRXTUNE 0xFC7FFFFF #define SCFG_QSPICLKCTLR 0x10 +#define DCSR_BASE 0x700000000ULL +#define DCSR_USB_PHY1 0x4600000 +#define DCSR_USB_PHY2 0x4610000 +#define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C +#define USB_PHY_RX_EQ_VAL_1 0x0000 +#define USB_PHY_RX_EQ_VAL_2 0x0080 +#define USB_PHY_RX_EQ_VAL_3 0x0380 +#define USB_PHY_RX_EQ_VAL_4 0x0b80 + #define TP_ITYP_AV 0x00000001 /* Initiator available */ #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ #define TP_ITYP_TYPE_ARM 0x0 -- 2.1.0.27.g96db324 _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
