On 26 July 2017 at 04:40, Philipp Tomsich <[email protected]> wrote: > The RK3368 has a somewhat temperamental BootROM (which I learned the > hard way) when it comes to reconfiguring the CPLL and GPLL (in fact, > experiments show that changing the GPLL broke things for me, while > changing the CPLL seems to be more benign). These should not be > modified by the SPL stage, if we intend to return to the BootROM for > chain booting the next stage. > > This commit changes the clock initialisation to not change CPLL/GPLL > before returning to the BootROM (i.e. in TPL). As it's safe to change > these settings if we no longer intend to return to U-Boot, we'll run > the full PLL setup a little later (i.e. in SPL). > > Signed-off-by: Philipp Tomsich <[email protected]> > --- > > Changes in v2: None > > drivers/clk/rockchip/clk_rk3368.c | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) >
Reviewed-by: Simon Glass <[email protected]> _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
