On 26 July 2017 at 04:40, Philipp Tomsich <[email protected]> wrote: > To implement a TPL stage (incl. its DRAM controller setup) for the > RK3368, we'll want to configure the DPLL (DRAM PLL). > > This commit implements setting the DPLL (CLK_DDR) and provides PLL > configuration details for the common DRAM operating speeds found on > RK3368 boards. > > Signed-off-by: Philipp Tomsich <[email protected]> > --- > > Changes in v2: None > > drivers/clk/rockchip/clk_rk3368.c | 35 +++++++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) >
Reviewed-by: Simon Glass <[email protected]> _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
