From: Patrice Chotard <patrice.chot...@st.com> Add RCC clock driver node and update all clocks phandle accordingly.
By default, on kernel side, all clocks was temporarly configured as a phandle to timer_clk waiting for a RCC clock driver to be available. On U-boot side, we now have a dedicated RCC clock driver, we can configured all clocks as phandle to this driver. All this binding update will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html Signed-off-by: Gabriel Fernandez <gabriel.fernan...@st.com> Signed-off-by: Patrice Chotard <patrice.chot...@st.com> --- arch/arm/dts/stm32h743-pinctrl.dtsi | 22 +++++++++++----------- arch/arm/dts/stm32h743.dtsi | 34 +++++++++++++++++++++++++++------- 2 files changed, 38 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi index 76bbd65..d438818 100644 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/dts/stm32h743-pinctrl.dtsi @@ -55,7 +55,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x0 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOA_CK>; st,bank-name = "GPIOA"; }; @@ -63,7 +63,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOB_CK>; st,bank-name = "GPIOB"; }; @@ -71,7 +71,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOC_CK>; st,bank-name = "GPIOC"; }; @@ -79,7 +79,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0xc00 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOD_CK>; st,bank-name = "GPIOD"; }; @@ -87,7 +87,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1000 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOE_CK>; st,bank-name = "GPIOE"; }; @@ -95,7 +95,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOF_CK>; st,bank-name = "GPIOF"; }; @@ -103,7 +103,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOG_CK>; st,bank-name = "GPIOG"; }; @@ -111,7 +111,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x1c00 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOH_CK>; st,bank-name = "GPIOH"; }; @@ -119,7 +119,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2000 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOI_CK>; st,bank-name = "GPIOI"; }; @@ -127,7 +127,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2400 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOJ_CK>; st,bank-name = "GPIOJ"; }; @@ -135,7 +135,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x2800 0x400>; - clocks = <&timer_clk>; + clocks = <&rcc GPIOK_CK>; st,bank-name = "GPIOK"; }; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index 36a99db..30b5cb4 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -42,30 +42,45 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" +#include <dt-bindings/clock/stm32h7-clks.h> / { clocks { clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0>; + clock-frequency = <25000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; }; - timer_clk: timer-clk { + clk_i2s: i2s_ckin { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <125000000>; + clock-frequency = <0>; }; }; soc { + rcc: rcc@58024400 { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "st,stm32h743-rcc", "st,stm32-rcc"; + reg = <0x58024400 0x400>; + clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; + st,syscfg = <&pwrcfg>; + }; + usart1: serial@40011000 { compatible = "st,stm32f7-usart", "st,stm32f7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; - clocks = <&timer_clk>; - + clocks = <&rcc USART1_CK>; }; usart2: serial@40004400 { @@ -73,14 +88,19 @@ reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; - clocks = <&timer_clk>; + clocks = <&rcc USART2_CK>; }; timer5: timer@40000c00 { compatible = "st,stm32-timer"; reg = <0x40000c00 0x400>; interrupts = <50>; - clocks = <&timer_clk>; + clocks = <&rcc TIM5_CK>; + }; + + pwrcfg: power-config@58024800 { + compatible = "syscon"; + reg = <0x58024800 0x400>; }; }; }; -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
