On 24 July 2017 at 03:44,  <patrice.chot...@st.com> wrote:
> From: Patrice Chotard <patrice.chot...@st.com>
>
> Add Driver Model support with use of generic DT
> compatible string "snps,dwc3"
>
> Signed-off-by: Patrice Chotard <patrice.chot...@st.com>
> ---
> v8:     _ Add CONFIG_DM_USB flag to fix compilation issue for platforms
>           which uses xhci-dwc3 driver and doesn't support yet driver model
>         _ fix bisection issue with this patch reported by Ɓukasz Majewski, 
> move struct
>           xhci_dwc3_platdata in patch 6 to fix it.
> v7:     _ add Reviewed-by
> v6:     _ remove useless struct xhci_dwc3
> v5:     _ replace dev_get_addr() by devfdt_get_addr()
> v4:     _ none
> v3:     _ none
> v2:     _ use dev_get_addr() and removed useless piece of code
>
>  drivers/usb/host/xhci-dwc3.c | 46 
> ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)

Reviewed-by: Simon Glass <s...@chromium.org>

Suggestion below.

>
> diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
> index 33961cd..0411826 100644
> --- a/drivers/usb/host/xhci-dwc3.c
> +++ b/drivers/usb/host/xhci-dwc3.c
> @@ -9,9 +9,15 @@
>   */
>
>  #include <common.h>
> +#include <dm.h>
> +#include <usb.h>
> +
> +#include "xhci.h"
>  #include <asm/io.h>
>  #include <linux/usb/dwc3.h>
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
>  void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
>  {
>         clrsetbits_le32(&dwc3_reg->g_ctl,
> @@ -97,3 +103,43 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
>         setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
>                         GFLADJ_30MHZ(val));
>  }
> +
> +#ifdef CONFIG_DM_USB
> +static int xhci_dwc3_probe(struct udevice *dev)
> +{
> +       struct xhci_hcor *hcor;
> +       struct xhci_hccr *hccr;
> +       struct dwc3 *dwc3_reg;
> +
> +       hccr = (struct xhci_hccr *)devfdt_get_addr(dev);

You should be able to use dev_read_addr() here.

Regards,
Simon
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