> The RK3368 has a somewhat temperamental BootROM (which I learned the
> hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
> experiments show that changing the GPLL broke things for me, while
> changing the CPLL seems to be more benign). These should not be
> modified by the SPL stage, if we intend to return to the BootROM for
> chain booting the next stage.
> This commit changes the clock initialisation to not change CPLL/GPLL
> before returning to the BootROM (i.e. in TPL). As it's safe to change
> these settings if we no longer intend to return to U-Boot, we'll run
> the full PLL setup a little later (i.e. in SPL).
> Signed-off-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
> Reviewed-by: Simon Glass <s...@chromium.org>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> drivers/clk/rockchip/clk_rk3368.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
Applied to u-boot-rockchip, thanks!
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