I am trying to migrate ECC Scheme, SYS_NAND_ECCBYTES,
SYS_NAND_ECCSIZE, and SYS_NAND_ECCSIZE to Kconfig with the changes
I am attaching.
I my ideal scenario, the selection of scheme would set
CONFIG_NAND_OMAP_ECCSCHEME to whatever menu option is defined, then
corresponding default values of CONFIG_SYS_NAND_ECCSIZE and
CONFIG_SYS_NAND_ECCBYTES, but I can't figure out how to make that
work.
When I run the migration tool, all the omap2plus boards fail.
If anyone has any suggestions, I'm open to ideas. I have been
testing this on the Logic PD DM3730 Kit.
Signed-off-by: Adam Ford <aford...@gmail.com>
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 75cbff9..a2e5a30 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -45,6 +45,54 @@ config NAND_OMAP_GPMC
do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
and BCH16 ECC algorithms.
+if NAND_OMAP_GPMC
+choice
+ prompt "OMAP ECC Scheme"
+ default OMAP_ECC_HAM1_CODE_SW
+
+config OMAP_ECC_HAM1_CODE_SW
+ bool "1-bit Hamming code using software lib. (legacy)"
+ help
+ 1-bit Hamming code using software lib.
+ (for legacy devices only)
+
+config OMAP_ECC_HAM1_CODE_HW
+ bool "1-bit Hamming code using GPMC hardware. (legacy)"
+ help
+ 1-bit Hamming code using GPMC hardware.
+ (for legacy devices only)
+
+config OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+ bool "8-bit BCH code w/ HW detection and SW correction"
+ depends on !NAND_OMAP_ELM
+ select BCH
+ help
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using software library.
+ - requires CONFIG_BCH to enable software BCH library
+ (For legacy device which do not have ELM h/w engine)
+
+config OMAP_ECC_BCH8_CODE_HW
+ depends on NAND_OMAP_ELM
+ bool "8-bit BCH code w/ HW detection and ELM engine"
+ help
+ 8-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+
+config OMAP_ECC_BCH16_CODE_HW
+ depends on NAND_OMAP_ELM
+ bool "16-bit BCH code w/ HW detection and ELM engine"
+ help
+ 16-bit BCH code with
+ - ecc calculation using GPMC hardware engine,
+ - error detection using ELM hardware engine.
+
+endchoice
+
+endif
+
config NAND_OMAP_GPMC_PREFETCH
bool "Enable GPMC Prefetch"
depends on NAND_OMAP_GPMC
@@ -170,6 +218,27 @@ config SYS_NAND_BUSWIDTH_16BIT
not available while configuring controller. So a static
CONFIG_NAND_xx
is needed to know the device's bus-width in advance.
+config SYS_NAND_ECCBYTES
+ int "ECC Bytes"
+ help
+ Defines the size and behavior of the NAND that SPL uses to read
U-Boot.
+ Number of ECC bytes generated to protect 512 bytes of data, which is:
+ 3 for HAM1_xx ecc schemes
+ 7 for BCH4_xx ecc schemes
+ 14 for BCH8_xx ecc schemes
+ 26 for BCH16_xx ecc schemes
+
+config SYS_NAND_ECCSIZE
+ int "ECC Size"
+ default 512
+
+config SYS_NAND_MAX_ECCPOS
+ int "maximum number of ECC bytes supported"
+ help
+ If specified, overrides the maximum number of ECC bytes
+ supported. Useful for reducing image size, especially with SPL.
+ This must be at least 48 if nand_base.c is used.
+
if SPL
config SYS_NAND_U_BOOT_LOCATIONS
diff --git a/lib/Kconfig b/lib/Kconfig
index 2f5a210..1194345 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -1,5 +1,12 @@
menu "Library routines"
+config BCH
+ bool "Enable Software based BCH ECC"
+ help
+ Enables software based BCH ECC algorithm present in lib/bch.c
+ This is used by SoC platforms which do not have built-in ELM
+ hardware engine required for BCH ECC correction.
+
config CC_OPTIMIZE_LIBS_FOR_SPEED
bool "Optimize libraries for speed"
help
--
2.7.4
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